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| 型號(hào)： | AN |
| 英文描述： | An overview of ZSP architecture |
| 中文描述： | ZSP架構(gòu)的一個(gè)概述 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 145K |
| 代理商： | AN |
1999 LSI Logic Corporation
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The ZSP Architecture has two MAC units that can work together or independently. Independently,
they can each perform a 16-bit by 16-bit multiply with a single 40-bit accumulation in a single cycle.
Together, they work to perform a single 32-bit by 32-bit multiply with 40-bit accumulation in a single
cycle. The MACs also contain hardware support for complex multiplies and the functionality to
perform a single-cycle add-compare-select for Viterbi decoding. The MACs also support parallel add
and parallel subtraction.
MAC operations affect the
v
(32-bit overflow),
gv
(40-bit overflow),
c
(carry) and
ge
(greater than or
equal to zero) flags, and results are immediately available in the next cycle for any other functional
unit while being written to the register file. There are “sticky” overflow flags for 32- and 40-bit
overflow conditions. The sticky flags can only be cleared by software. The Functional Mode register
controls most MAC operations in terms of rounding, saturation on overflow, and fractional number
support.
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The ZSP Architecture provides two identical 16-bit ALUs that can work independently in parallel or
together to form a single 32-bit ALU. In addition to traditional ALU functionality, these ALUs also
provide bit manipulation and normalization capability.
All ALU operations are single-cycle, and affect the
gt
(greater than zero),
ge
(greater than or equal
to zero),
z
(zero),
v
(overflow) and
c
(carry) flags. The result of any ALU operation is available for
any functional unit on the next cycle while being written to the register file. The Functional Mode
register controls rounding, saturation, and fractional number support of most ALU operations.
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There are two types of register files: the operand register file (ORF) and the control register file
(CRF). All registers are 16-bit, memory-mapped, and can be read or written by the user.
The operand register file (ORF) has a total of sixteen 16-bit registers. Any of these registers may be
used as the input or output of any ALU operation, or as a pointer to memory for register indirect
addressing. For MAC and MUL instructions, all the registers can be used as input but only a subset of
these can be destination registers. In addition, any operand register may be used as a stack pointer.
The registers are denoted by
rX
, where 0
≤
X
≤
15. The ORF is accessed via load/store instructions.
The ZSP
Architecture also provides support for extended precision (32-bit) operations. In these
operations (typically denoted in the instruction set with a “
.e
” extension), registers are used in pairs
and are referenced by the lower, even numbered register. For example, the instruction
add.e r2, r4
describes the addition of the 32-bit operands contained in register pairs {r3 r2} and {r5 r4}. The
result of this operation is stored in {r3 r2}.
The control register file (CRF) provides mode control as well as status and flag information. The CRF
contains thirty-two 16-bit registers.
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