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| 型號： | AN |
| 英文描述： | An overview of ZSP architecture |
| 中文描述： | ZSP架構(gòu)的一個概述 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 145K |
| 代理商： | AN |
1999 LSI Logic Corporation
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The ZSP Architecture offers the optimum solution for many next-generation DSP applications. The
Architecture leverages design techniques from advanced microprocessors and is optimized for digital
communications and wireless network applications.
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Superscalar DSP architecture
Dispatches up to four instructions per cycle
Dual Multiply Accumulate (MAC) and dual Arithmetic Logic Unit (ALU)
Short five-stage pipeline minimizes penalties of branch misprediction
RISC-based instruction set architecture: ALL instructions execute in a single cycle
Fixed-length instructions allow efficient pre-fetch and decoding to increase throughput
Load/Store architecture: De-couples load and store operations from instructions
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Register-based orthogonal instruction set
Highly programmable: compiler AND programmer friendly
Familiar programming paradigm minimizes software risk
Hardware scheduling: eliminates conflicts and ensures deterministic behavior
Compiler produces efficient DSP assembly from high-level languages
Hardware caches and pre-fetch logic minimize programmer exposure to memory access
bottlenecks
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High code efficiency: High performance without unrolling inner loops
Microprocessor-based programming paradigm for control applications
Efficient context save and a multi-level interrupt structure for multitasking
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High performance enables programmable solutions for new applications
Hidden pipeline enables software compatibility across ZSP Processor families
Scalable: Architecture may be reconfigured for varying processing needs without affecting the
programming model
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