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參數(shù)資料
| 型號(hào)： | AN8041S |
| 廠商： | PANASONIC CORP |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | Liquid crystal backlight control IC |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO16 |
| 封裝： | PLASTIC, SOP-16 |
| 文件頁(yè)數(shù)： | 5/15頁(yè) |
| 文件大小： | 153K |
| 代理商： | AN8041S |
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5
Voltage Regulators
AN8041S
Pin No.
Equivalent circuit
Description
I/O
4
DTC:
The terminal for connecting a resistor and ca-
pacitor to set the dead-time and soft start period
of PWM output. Input current I
DTC
is determined
by the timing resistor R
T
, so that dispersion and
fluctuation with temperature are suppressed. It
is approx.
12.3
μ
A when R
T
=
15 k
.
V
RT
×
1
[A]
R
T
2
I
DTC
=
5
S.C.P.:
The terminal for connecting a capacitor to set the
time constant of soft start and timer latch short-
circuit protection circuit.
Use a capacitance value in the range of more than
1 000 pF.
The charge current I
CHG
is determined by the
timing resistor R
T
, so that dispersion and fluc-
tuation with temperature are suppressed. It is
approx.
1.3
μ
A when R
T
=
15 k
.
I
CHG
=
V
RT
×
[A]
R
T
11
IN
+
1:
The noninverted input terminal of the error am-
plifier 1.
For common-mode input, use in the range of
0.1 V to
+
0.8 V.
IN
1:
The inverted input terminal of the error ampli-
fier 1.
For common-mode input, use in the range of
0.1 V to
+
0.8 V.
1
6
I
7
I
8
FB1:
The output terminal of the error amplifier 1.
Source current: approx.
120
μ
A
Sink current
: approx. 8 mA
Correct the frequency characteristics of the gain
and the phase by connecting a resistor and a ca-
pacitor between this terminal and IN
1 terminal.
O
9
FB2:
The output terminal of the error amplifier 2.
Source current: approx.
120
μ
A
Sink current
: approx. 8 mA
Correct the frequency characteristics of the gain
and the phase by connecting a resistor and a ca-
pacitor between this terminal and IN
2 terminal.
O
I
Terminal Equivalent Circuits (continued)
Q
S
Latch
0.75 VR
V
REF
I
CHG
To U.V.L.O.
5
V
REF
6
7
V
REF
8
Source current
Sink current
V
REF
9
Source current
Sink current
V
REF
PWM
comparator
input
I
DTC
C
DTC
R
DTC
4
RT
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