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參數(shù)資料
| 型號(hào)： | AN734 |
| 廠商： | Vishay Intertechnology,Inc. |
| 英文描述： | Design Guidelines for the Low-Noise Low-Dropout Regulator Si9181 |
| 中文描述： | 為設(shè)計(jì)準(zhǔn)則低噪聲低壓差穩(wěn)壓器Si9181 |
| 文件頁數(shù)： | 5/5頁 |
| 文件大小： | 47K |
| 代理商： | AN734 |
AN734
Vishay Siliconix
Document Number: 71337
31-Oct-00
www.vishay.com
5
DYNAMIC LOAD RESPONSE
The ability to use a low ESR ceramic capacitor at the output of
the Si9181 helps reduce the glitch during the high slew-rate
step load, while the high closed loop bandwidth reduces the re-
covery time. With a 2.2- F ceramic capacitor at the output, the
maximum deviation observed in the output is 30 mV, with bet-
ter than 3- S recovery time. Refer to the Figures 5 and 6. The
recovery time of the output from overshoot during the load re-
moval is the time required to discharge the output capacitor.
The recovery time depends on the voltage overshoot, capaci-
tor and the load current.
Figure 5.
Load Transient Response-1
I
100 mA/div
V
10 mV/div
V
OUT
= 3.3 V
C
IN
C
OUT
= 2.2 F
I
LOAD
= 1 to 150 mA
t
rise
= 2 sec
Figure 6
. Load Transient Response-2
V
OUT
= 3.3 V
C
IN
C
OUT
= 2.2 F
I
LOAD
= 150 to 1 mA
t
fall
5.00 s/div
I
100 mA/div
V
10 mV/div
5.00 s/div
PCB LAYOUT
The component placement around the LDO should be done
carefully to achieve good dynamic line and load response. The
input and noise capacitor should be kept close to the LDO. The
rise in junction temperature depends on how efficiently the
heat is carried away from the junction to ambient. The junction
to lead thermal impedance is a characteristic of the package
and is fixed. The thermal impedance between lead to ambient
can be reduced by increasing the copper area on PCB. In-
crease the input, output and ground trace area to reduce the
junction-to-ambient thermal impedance.
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