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參數(shù)資料
| 型號(hào)： | AN734 |
| 廠商： | Vishay Intertechnology,Inc. |
| 英文描述： | Design Guidelines for the Low-Noise Low-Dropout Regulator Si9181 |
| 中文描述： | 為設(shè)計(jì)準(zhǔn)則低噪聲低壓差穩(wěn)壓器Si9181 |
| 文件頁(yè)數(shù)： | 3/5頁(yè) |
| 文件大小： | 47K |
| 代理商： | AN734 |
AN734
Vishay Siliconix
Document Number: 71337
31-Oct-00
www.vishay.com
3
PROTECTION FEATURES
Short circuit
In the event of a short circuit in the equipment powered by an
LDO, the Si9181 limits the maximum current to prevent dam-
age to the electronics. The peak current through the Si9181 is
typically limited to 800 mA during a continuous short circuit at
the output.
Over-Temperature
The Si9181 is designed with an over temperature protection
circuit to prevent thermal runaway in the p-channel power
MOSFET. If the temperature reaches 165 C, the internal con-
trol circuit shuts off the p-channel power MOSFET. The LDO
will remain disabled until the chip temperature drops below
145 C, and will re-engage automatically. The 20 C tempera-
ture difference avoids possible oscillation and reduces the av-
erage power delivery during fault conditions to reduce the risk
of damage.
LOOP COMPENSATION
For the stable operation of a closed loop electronic system,
such as a voltage regulator, the feedback loop needs to be
compensated to keep the total phase lag at less than 360 for a
signal having the total gain more than or equal to unity. The
phase lag includes the 180 phase change caused by the neg-
ative feedback.
The Si9181 equivalent circuit and its gain characteristic with
internal compensation is shown in Figure 3. The closed loop
has two low frequency poles. A low frequency pole (P
O
) is a
result of output capacitance C
OUT
and the channel length
modulation parameter of the P-MOS. The location of this
pole changes with the load current, I
O
.
P
O
I
O
C
OUT
2
(4)
The second pole is introduced by the compensation capaci-
tance Cc, parasitic capacitance of the series pass element and
the error amplifier. The error amplifier output impedance
r
and the compensation capacitor along with the gate capaci-
tance of PMOS determine the location of the second pole P
p
.
The gate capacitance is low enough to be neglected here.
P
p
1
2 r
O
C
c
(5)
The Si9181 uses an internal zero to achieve a stable feedback
loop, eliminating the need to rely on the ESR value of the out-
put capacitors for a zero. The location of internal zero Z
c
is
changed to offset any effect of the load on the low frequency
pole P
O
. This internal zero also offers the freedom to use a
low
–
ESR ceramic X5R or Y5V capacitor for lower noise.
Z
ESR
1
2
C
O
ESR
(6)
With the native compensation of the Si9181, a closed
–
loop
bandwidth as high as 100 kHz can be achieved easily with a
phase margin no lower than 60 . (See Figure 4.
)
FIGURE 3.
Loop Compensation
Gain
P
O
Z
c
Z
ESR
Frequency
Output V
O1
Ref
Input
Com
ro
C
OUT
ESR
R
LOAD
Rc
Cc
P
P
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