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參數(shù)資料
| 型號： | AN709 |
| 廠商： | Vishay Intertechnology,Inc. |
| 英文描述： | LJT 4C 4#20 SKT RECP |
| 中文描述： | 與Si9976DY ?設(shè)計通道半橋驅(qū)動器和雙MOSFET的小腳 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 86K |
| 代理商： | AN709 |
AN709
Vishay Siliconix
Document Number: 70582
15-Jun-00
www.vishay.com FaxBack 408-970-5600
3
Part
Number
r
DS(on)
Q
g
@
V
GS
= 10 V
(nC)
Minimum
Recommended
C
BOOT
( F)
Si4946EY
0.055
30
0.039
Si9945
0.10
15
0.018
Table 1 shows the selected bootstrap capacitor for each
MOSFET was selected using the method described, with a
switching frequency of 20 kHz.
If a shorter recharge time is required, an external signal diode
can be added from V
DD
to the positive side of the bootstrap
capacitor (CAP). This increases the charging current,
especially at the lower values of V+. Also, the value of the
capacitor on V
DD
should be increased, since this is the source
of the additional charging current.
The low-side drive circuitry operates directly from V
DD
and
does not have recharge requirements. The capacitor
connected to V
DD
supplies the charge required to turn on the
low-side MOSFET. It must be sized to ensure that V
DD
does
not drop below 14 V, which would trigger an undervoltage
condition. As in the case of the bootstrap capacitor, the V
DD
bypass capacitor should be sized such that it will hold 10 times
the charge required by the MOSFET at a V
GS
= 10 V (C = 10
x Q
g
/V
GS
). The Si9945 requires a 15-nC charge for turn on with
V
GS
= 10 V. Therefore, a 0.018 F capacitor will work well.
Since the requirements for value selection are the same as for
the bootstrap capacitor, the recommended values in Table 1
also apply to the V
DD
bypass capacitor. If an external bootstrap
diode is used to reduce the bootstrap capacitor recharge time,
the value of the V
DD
bypass capacitor should be doubled. This
compensates for the additional load of recharging the
bootstrap capacitor and prevents the occurrence of an
undervoltage condition.
Turn-on delays have been incorporated to prevent cross
conduction of the half-bridge MOSFETs (Figure 3). The
high-side MOSFET can be turned on only after a 250-ns time
delay, which is initiated by the low-side output, G2, switching
to ground. The low-side MOSFET can be turned on only after
a 300-ns delay which is initiated by the high-side control logic.
These delays prevent one half-bridge MOSFET from turning
on before the other is completely turned off. The difference in
the method of generating the delays occurs because the
high-side output, G1, is level shifted with respect to S1.
High Side
Logic
G
1
G
2
Figure 3.
Cross Conduction Protection
250 ns
Delay
Low Side
Logic
300 ns
Delay
IN
EN
During power up, both MOSFETs are held off until the internal
power supply, V
DD
, is within approximately 0.7 V of the final
value, which is nominally 16 V. After power up, the low-side
undervoltage lockout circuitry, UVL2, continues to monitor
V
DD
. If an undervoltage condition occurs, both the high-side
and the low-side MOSFETs will be turned off, and the FAULT
output will be high. When the undervoltage condition no longer
exists, the FAULT output will be cleared and normal function
will resume.
A separate undervoltage lockout circuit, UVL1, monitors the
bootstrap voltage. If an undervoltage condition exists when the
IN line is switched high, this circuit will prevent the high-side
MOSFET from turning on. In addition, one of the following
conditions will exist. If S1 is high (as the result of inductive
flyback current through the high-side MOSFET’s body-drain
diode or a short from S1 to V+), the high-side MOSFET will be
allowed to turn on as soon as the undervoltage condition has
been removed. If S1 is low, the high-side MOSFET will be
allowed to turn on only after the undervoltage condition has
been removed and the IN line has been toggled low and back
to high.
If the load voltage, S1, does not make the intended transition
through V
DD
to either ground or V+ before a specified time,
the Si9976DY sees this as an output short circuit (Figure 4).
The transition should take place in less than 300 ns for a
transition to V+, and 200 ns for a transition to ground. Detection
of a short circuit condition latches both outputs off and the fault
line high. The outputs are re-enabled by a rising edge on the
enable line, EN.
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