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參數(shù)資料
| 型號： | AN5394FB |
| 廠商： | PANASONIC CORP |
| 元件分類： | 消費家電 |
| 英文描述： | RGB processor IC for the HDTV(Japan) and wide-screen TV |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | 12 X 12 MM, PLASTIC, QFP-48 |
| 文件頁數(shù)： | 32/33頁 |
| 文件大?。?/td> | 238K |
| 代理商： | AN5394FB |
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AN5394FB
ICs for TV
32
I
Application Note (continued)
2. I
2
C bus control contents (continued)
5) V-latch operation
(Function) The data for sub-address 00 to 03 remains unchanged until VP pulse comes.
6) Auto increment: This IC performs the designation of sub address by using the lower 5 bits. The uppermost bit is
used for designation of auto increment.
When the sub address uppermost bit is defined as 0 (sub address: 00 to 19 HEX)
The sequential data transfer leads to the sequential change of sub address, then the data is inputted.
The data is inputted as above. But the data will be invalid after sub address 1A.
When the sub address uppermost bit is defined as 1 or sub address is 80 to 99 HEX, the sequential data transfer
leads to data input on the same address.
I
2
C bus
VP
IC ouput
Data 1
Data 2
Old data
Data 1
transfer
Data 2
transfer
I
2
C bus
transfer
Data
1
Data
2
Data
3
Sub address
X
X
+
1
X
+
2
Input data
Data 1
Data 2
Data 3
Sub address
X
Slave
address
I
2
C bus
transfer
Data
1
Data
2
Data
3
Sub address
8Y
8Y
8Y
Input data
Data 1
Data 2
Data 3
Sub address
8Y
Slave
address
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