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參數(shù)資料
| 型號(hào)： | AN5394FB |
| 廠(chǎng)商： | PANASONIC CORP |
| 元件分類(lèi)： | 消費(fèi)家電 |
| 英文描述： | RGB processor IC for the HDTV(Japan) and wide-screen TV |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | 12 X 12 MM, PLASTIC, QFP-48 |
| 文件頁(yè)數(shù)： | 25/33頁(yè) |
| 文件大?。?/td> | 238K |
| 代理商： | AN5394FB |
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ICs for TV
AN5394FB
25
DAC name
bit Sub
Data address(H)
Operation
Remarks
address(H)
( )Standard status
Color control
7
00
00 to (40) to 7F
Chroma amplitude upped with
With V latch
data upped Complete iris of
data(00) color with
→
Refer to "(5) V latch op-
eration" in
I
Application Note
for details.
With V-latch
Tint control
7
01
00 to (40) to 7F
Direction to make the flesh
tone red with data(00)
Direction to make the flesh
tone green with data(7F)
Pedestal upped with data
upped
Brightness
control
Contrast control
8
02
00 to
(80) to FF
With V-latch
7
03
00 to (40) to (7F)
Signal amplitude upped with With V-latch
data upped complete iris of
color with data(00)
Drive (R)
8
04
00 to (40) to 7F
R gain upped with data upped
Drive (G)
8
05
00 to (40) to 7F
G gain upped with data upped
Drive (B)
8
06
00 to (40) to 7F
B gain upped with data upped
Cufoff (R)
8
+
07
+
0A
(00) to 80 to FF
2SW
00 to (80) to C0
I
Application Note (continued)
2. I
2
C bus control contents
1) I
2
C bus protocol
2) Slave address
The slave address of this IC is 84H.
3) Since the data status at power on is not guaranteed, be sure to send data to all addresses before using.
4) Sub-address data
S
Slave address
O
A
Sub address
A
Data byte
A
P
Start condition
Write
Acknowledge bit
Stop condition
30LSB
30LSB
30LSB
FF
2.0 V
00
00
07
0A
00
C0
FF
00
FF
00
80
40
FF
Cutoff (R)
R
R-out pedestal is
upped with data up
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