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參數(shù)資料
| 型號(hào)： | AN5295NK |
| 廠商： | PANASONIC CORP |
| 元件分類(lèi)： | 音頻控制 |
| 英文描述： | 3-ch. sound signal processing single chip IC for TV with I2C bus |
| 中文描述： | 3 CHANNEL(S), TONE CONTROL CIRCUIT, PDIP30 |
| 封裝： | 0.400 INCH, PLASTIC, SDIP-30 |
| 文件頁(yè)數(shù)： | 10/11頁(yè) |
| 文件大小： | 121K |
| 代理商： | AN5295NK |
AN5295NK
ICs for TV
10
I
Technical Information (continued)
I
2
C bus (continued)
2. I
2
C bus transfer sequence
Two type of transfer messages of SCL and SDA are sent by synchronous serial transfer. SCL is a clock of
constant frequency and SDA indicates address data to control receiving side and is sent in parallel by synchroniz-
ing with SCL. Data are transferred in principle with 8-bit 3 octet (byte) and acknowledge bit exists every one octet.
Frame organization are described as follows:
1) Start condition
When SDA becomes low from high at SCA
=
high, receiver is on a data receiving mode.
2) Stop condition
When SDA becomes high from low at SCA
=
high, receiver stops receiving data.
3) Slave address
Address determined by device. Receiving is stopped when address of another device is sent.
4) Sub address
Address determined by function
5) Data
Data to control
6) Acknowledge bit
To let the master acknowledge that data has been received for each octet in such manner
that the master sends a high signal and the receiver sends back a low signal as shown by
above transfer sequence.
SDA is not changed when SCL is high except start and stop conditions.
3. Sub address byte and data byte format
Start
condition
SDA
SCL
Stop
condition
Slave address
Sub address
Data
Acknowledge
bit
Acknowledge
bit
Transfer message example
Acknowledge
bit
1 0 0 0 0 0 0 0
0 0 0 0 0 0 1 0
0 0 0 1 0 0 1 0
8
0
0
2
1
2
Sub
address
Upper MSB
Data byte
D7
D6
D5
D4
D3
D2
D1
D0
00
L-ch. vol.
Mute on/off
AGC on/off
01
R-ch. vol.
C-ch. mute
on/off
Surround
on/off
02
C-ch. vol.
Bass mix.
on/off
C-In select
03
L/R/C treble
L/R/C bass
04
0
0
0
0
0
0
0
0
05
Surround effect
Surround loop
on/off
0
0
DAC1
L/H
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