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參數(shù)資料
| 型號： | AN5177 |
| 英文描述： | Improve gate drive for GTO series connections |
| 中文描述： | 改善GTO的系列連接?xùn)艠O驅(qū)動(dòng) |
| 文件頁數(shù)： | 3/5頁 |
| 文件大?。?/td> | 96K |
| 代理商： | AN5177 |
3/5
AN5177 Application Note
www.dynexsemi.com
Fig. 4 Loop inductance and dynamic resistance
IMPROVED GATE DRIVE UNIT TURN-OFF
PERFORMANCE
A new gate drive unit(GDU) has been designed which gives the
GTO improved turn-off performance.
Figure 3 shows a simplified circuit of the turn-off section of the
GDU. The turn-off current pulse is achieved by charging a
parallel bank of low inductance capacitors to 20 volts and
discharging into the GTO gate using MOSFET switches. To
achieve a high current and high dIg/dt a low loop inductance is
required.
LOOP INDUCTANCE AND DYNAMIC RESISTANCE
The relevant parts of the loop inductance and dynamic resistance
are shown in figure 4.
Unfortunately, the physical design of the GTO itself, with its
centre gate and gate termination layout, limits the minimum loop
inductance which can be achieved. However, careful design of
the gate drive PCB and of the interconnecting lead to the GTO
housing has resulted in a great reduction in the overall loop
inductance. For the GTO type DGT409 a loop inductance of less
than 65nH has been achieved. This compares with 500nH for the
conventional GDU and lead switching at 40A/
μ
s and around
15nH for the IGCT.
Conventionally, coaxial type cable is used as the gate lead to
GTOs but the inductance of a normal cable and its terminations
is too high for our application. To minimise the mutual inductance
of a connecting lead pair it is necessary to keep the spacing
between the forward and return lead as small as possible. A
coaxial cable is better than a twisted pair but the strip line is
probably the best. Here the conductors are usually thin copper
sheets separated by a very thin insulating sheet.
The effective inductance of a conductor is, in part, determined by
the operating frequency. The dynamic resistance of a lead is
increased at high operating frequencies by the ‘skin’ effect i.e.
the tendency of high frequency currents to flow near the outer
surface of a conductor. For this reason, strip line with its high
surface area to cross sectional area ratio is an ideal choice for
high current pulses with fast rising and falling edges.
PERFORMANCE IMPROVEMENTS IN THE GTO
AT GATE TURN-OFF
The performance improvements reported below are for a standard
DGT409 which is a reverse blocking GTO type.
In measuring the effects on GTO performance of high dig/dt gate
turn off, three areas are of key importance.
1. The effect on turn-off switching loss.
2. The effect on turn-off current rating, Itcm.
3. The effect on storage time.
1. Figure 5 shows the increase in turn-off switching loss with
dI
/dt However, at high dI
/dt values, above about 50A/
μ
S,
the rate of increase is low so the loss penalty for using high
dIgt/dt values is small.
2. The effect on I
is beneficial. The high dI
/dt and peak turn-
off current ensure that the elements most remote from the
gate connection on the edge of the silicon slice receive more
gate current than normal. This means that the storage time
variations between the elements is much less and sharing of
turned off current between elements is much better.
Figure 6 shows the variation of I
TCM
with Cs for normal and high
dI
GT
/dt.
3. The reduction in storage time, t
, is very marked between
dI
/dt = -40A/
μ
s and –250A/
μ
s, typically a factor of 6. It
follows that as
t
also reduces by a factor of 6 then Cs can
be reduced by the same factor for the same change in
V.
Figure 7. However, by the law of diminishing returns further
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