參數(shù)資料
型號: AN5095
廠商: Panasonic Corporation
英文描述: Single chip IC with I2C bus interface for PAL/NTSC color TV system
中文描述: 單一的PAL制式的I2C總線接口芯片IC / NTSC彩色電視系統(tǒng)
文件頁數(shù): 32/36頁
文件大小: 405K
代理商: AN5095
32
AN5095K
ICs for TV
I
Technical Information (continued)
Explanation of each block (continued)
6. Jungle (continued)
3) Built-in frequency discrimination circuit: The circuit outputs the judgment results of 50 Hz/60 Hz in accor-
dance with the frequency of the vertical synchronizing signal.
(60 Hz
high)
45
Input frequency
Judgement
Output voltage
4) The output holds the previous state when the input frequency is 45 Hz or less and 65 Hz or more, and the
output changes for the first time when judged as 50 Hz or 60 Hz for 3 consecutive vertical periods.
5) The horizontal detection circuit and X-ray protection circuit (shut-down method) are built in.
6) The screen center position is adjustable by the I
2
C bus. (
±
1.6
μ
s)
7) For the blue-back in a weak electric field, the stable screen image is held by the vertical trigger off mode ( I
2
C
bus).
7. I
2
C bus
1) Incorporating 14 DAC controls and 12 SWs for eliminating the need for the adjustment of set mechanism.
2) Provided with automatic increment function.
Sub address 0 *: Automatic increment mode.
(When data are sent in regular succession, sub address changes successively and data are inputted.)
Sub address 8 *:
(When data are sent in regular succession, data are inputted with the same sub address.)
3) I
2
C Bus Protocol
Slave address: 10 001 010 (8AH)
Slave address format
S
Slave address
0
A
Sub address
A
Data byte
A
P
Start
condition
Write
Acknowledge bit
Stop
condition
4) Sub address byte and data byte format
The description in ( ) shows the initial state.
Data byte
D4
Sub address
D7
P/N
D6
PN/S
(0
PN)
Ver. TRG
(0
normal)
D5
D3
D2
D1
D0
00
Color
(21H)
01
(21H)
02
(41H)
03
(21H)
04
(81H)
05
(81H)
06
(81H)
(0
P)
Ver. auto
(0
auto)
Ver. OSC
(0
50)
SIF
SW
Tint
Brightness
Video
SW
Contrast
Cut off R
Cut off G
Cut off B
Hold
55
65
Hold
50 Hz
(Low)
(High)
60 Hz
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