參數(shù)資料
型號： AN5095
廠商： Panasonic Corporation
英文描述： Single chip IC with I2C bus interface for PAL/NTSC color TV system
中文描述： 單一的PAL制式的I2C總線接口芯片IC / NTSC彩色電視系統(tǒng)
文件頁數(shù)： 10/36頁
文件大?。?/td> 405K
代理商： AN5095
10
AN5095K
ICs for TV
I
Electrical Characteristics at T
a
=
25
°
C (continued)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
RGB processing circuit (continued)
DAC data are typicals
External R, G, B frequency
characteristic
f
RGBC
Input 0.2 V[p-p]
8
10
MHz
Internal and external R, G, B
output voltage ratio
V
E/I
External part 0.7 V[p-p]/internal part
0.6 V[p-p] input, contrast 03
=
20 (typ.)
0.78
0.92
1.06
Time
Synchronizing signal processing circuit
Horizontal free run frequency
f
HO
τ
HO
Without sync. signal input
15.33 15.63 15.93
kHz
Horizontal output pulse duty cycle
Upward pulse duty cycle
31
37
43
%
Horizontal pull-in range
f
HP
f
VO-P
Difference from f
H
=
15.625 kHz
Data 01-D7
=
1, 02-D7
= 0,
forced
50 Hz mode, without sync. signal input
±
500
±
650
Hz
PAL horizontal free run frequency
48
50
52
Hz
NTSC vertical free run frequency
f
VO-N
Data 01-D7
=
1, 02-D7
= 1,
forced
60 Hz mode, without sync. signal input
58
60
62
Hz
Vertical output pulse width
τ
VO
For both PAL/NTSC
9
10
11
1/fH
PAL vertical pull-in range
f
VPP
f
H
=
15.625 kHz, forced 50 Hz mode
f
H
=
15.75 kHz, forced 60 Hz mode
46
3.1
4.2
54
Hz
NTSC vertical pull-in range
f
VPN
56
64
Hz
Horizontal high-level output voltage
V
56H
High-level DC voltage
2.8
3.4
V
Horizontal low-level output voltage
V
56L
Low-level DC voltage
0.3
V
Vertical high-level output voltage
V
58H
High-level DC voltage
3.9
4.5
V
Vertical low-level output voltage
V
58L
T
HC
Low-level DC voltage
0.3
V
Screen center variable range
Change amount of phase difference between
sync. and H-out of data 0B
=
40 to 47
2.6
3.2
4.4
μ
s
Overvoltage protection operation V
X-RAY
voltage
The pin 55 minimum voltage at which
H-out does not appear any longer
0.60
0.68
0.76
V
Vertical frequency
discrimination (50)
f
50
Vertical frequency at which V
5
becomes
low (
<
0.5 V)
47
55
Hz
Vertical frequency
discrimination (60)
f
60
Vertical frequency at which V
5
becomes
high (
>
4.5 V)
57
63
Hz
Synchronous signal clamp voltage
V
46
V
fHS
V
46
clamp voltage
The minimum V
50
at f
0
>
10 kHz
and horizontal oscillation output is
higher than 1 V[p-p]
1.1
1.4
1.7
V
Horizontal output start voltage
3.4
4.2
5.0
V
I
2
C interface
Sink current when ACK
I
ACK
The maximum value of pin 21 sink
current at ACK
1.5
2.0
5.0
mA
SCL, SDA signal high level input
V
IHI
3.1
V
SCL, SDA signal low level input
V
ILO
f
Imax
0.9
V
Allowable maximum input
frequency
100
kbit/s
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