- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄362332 > AN4058 MA31750 - Pipelining instructions PDF資料下載
參數(shù)資料
| 型號(hào)： | AN4058 |
| 英文描述： | MA31750 - Pipelining instructions |
| 中文描述： | MA31750 -流水線指令 |
| 文件頁(yè)數(shù)： | 1/2頁(yè) |
| 文件大?。?/td> | 32K |
| 代理商： | AN4058 |
MA31750 - Application Note 15
1/2
2.0 PIPELINING ON THE MA31750
3.0 EXAMPLE
When analysing the behaviour of the MA31750, the pipelining of instructions must be considered.
1.0 PIPELINING INSTRUCTIONS
The pipeline on the MA31750 always holds 2 16-bit words.
If the instruction being executed is a single word instruction,
then only one word has been removed from the pipeline. The
second word in the pipeline moves up to the first position and
one extra word is pre-fetched from system memory. If the
instruction being executed is a double word instruction, then
the pipeline has emptied and two pre-fetches are necessary to
fill it up again.
Occasionally the pipeline needs emptying and reloading,
eg. after initialisation or after an interrupt service routine or if a
branch or jump is executed. This will take 2 machine cycles
dedicated to pre-fetching the new pipeline. Execution can then
resume.
Instructions are pre-fetched from system memory and are
stored in the pipeline of the processor. They are then pulled
from the pipeline to be executed. Whilst the instructions are
being executed, the pipeline has emptied and the pre-fetch of
the next instruction can take place. This pre-fetch is limited to
times when the system address and data busses are free as it
utilises these busses to access the system memory. See
Figure 1.
A[0:15]
D[0:15]
0000
0001
0002
0003
0004
0005
E500
8510
FFFF
9010
4000
E511
0006
E500
4000
0007
FFFF
E522
1
2
3
4
5
6
7
8
9
cycle no.
Figure 1: Example of Operation
Figure 1 shows the address and data busses for the
following code:
0000
0001
0003
0005
0006
0007
E500:
8510 FFFF:
9010 4000:
E511:
E500:
E522:
XORR R0,
LIM
ST
XORR R1,
XORR R0,
XORR R2,
R0
FFFF
4000
R1
R0
R2
R1,
R1,
Cycles 1 and 2 are used to fill the pipeline. No instruction
execution occurs.
On cycle 3, the XORR instruction is taken from the pipeline
and the registers are exor'ed internally. At the same time, the
data from address 0002 is loaded into the pipeline.
The next instruction in the pipeline is a double word
instruction, therefore cycles 4 and 5 are both needed to refill
the pipeline. Whilst the data from addresses 0004 and 0005
are being pre-fetched, register 1 is loaded across internal
busses with data FFFF.
Again, the pipeline contains a double word instruction, so
cycles 6 and 7 are both needed to refill the pipeline. However,
the store instruction needs to use the external address and
data busses. This is done on cycle 8 after the pre-fetches have
finished.
Once the store has completed, the next instruction is
executed. This is a single word instruction (XORR), hence
cycle 9 is used for the pre-fetch, as the exor instruction is
executed internally.
AN4058
MA31750 - Pipelining Instructions On The MA31750
Application Note
An4058-2.1 July 2002
Replaces July 2000 version, AN4058-2.0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AN4502 | Electrostatic handling precautions |
| AN4503 | An introduction to IGBTs |
| AN4504 | IGBT ratings and characteristics |
| AN4507 | Gate drive considerations to maximise IGBT efficiency |
| AN5011 | TV Channel Selector Circuit |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AN40-N04 | 制造商:SMC Corporation of America 功能描述:Silencer, Compact Resin, Male Thread, 1/2" NPT Port, 30 dB(A), 68mm, Model AN40 |
| AN4105 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Design Considerations for Switched Mode Power Supplies Using A Fairchild Power Switch (FPS) in a Flyback Converter |
| AN4107 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Design of Power Factor Correction |
| AN410A | 制造商:n/a 功能描述:Ships in 2 days |
| AN4-10A | 制造商:AN# - MILITARY 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。