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參數(shù)資料
| 型號： | AN2701 |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 英文描述： | PWM Generation with the HC08 Timer |
| 中文描述： | PWM生成與HC08的計時器 |
| 文件頁數(shù)： | 8/14頁 |
| 文件大?。?/td> | 158K |
| 代理商： | AN2701 |
Channel 1: PWM signal generated
Channel 2: Events
PWM Generation with the HC08 Timer, Rev. 0
8
Freescale Semiconductor
PWM Generation
Figure 4. Set on Output Compare
The major advantage of this method is that it works separately from the CPU activity and the rest of the
software.
However, it also means the timer used for the PWM generation has its modulo counter (i.e. signal period)
fixed for all its other channels. Therefore, generation of multiple signals with different periods will be
impossible on the same module; only different duty cycles will be possible.
Flexible PWM Rolling Generation
Principle
The solution described above is easy to set up and use, but could lack flexibility.
Using the following method will increase the possibility that the timer can generate any PWM signal on
any channel. However, it will also increase the complexity and size of the code.
The principle used here is to not rely on the modulo counter to determine the period, as only one is
available for all channels of the same timer.
References to the master timer modulo register, TxMODH:TxMODL, are avoided by simply adding
consecutive mark (logic 1) and space (logic 0) values to the timer compare register on successive ISR
function calls, as shown in the following equations. Timer roll-over is seamless when using unsigned
integer addition. Using the previous compare value as a reference for generating the next compare value
allows precise output timing, even though the ISR latency may vary.
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