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| 型號： | AN211A |
| 廠商： | Motorola, Inc. |
| 英文描述： | FIFELD EFFECT TRANSISTORS IN THEORY AND PRACTICE |
| 中文描述： | FIFELD場效應(yīng)晶體管理論與實踐 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大小： | 340K |
| 代理商： | AN211A |
9
MOTOROLA SEMICONDUCTOR APPLICATION INFORMATION
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iss
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Figure 18. Recommended C
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Figure 19. Typical Variations of FET Noise Figure with
Frequency and Source Resistance
r
ds(on)
the channel in series with the drain and source. From an
applications standpoint, it is important primarily for switching
and chopper circuits since it affects the switching speed and
determines the output level. To complete the confusion of
multiple symbols for FET parameters, channel resistance is
sometimes indicated as r
d(on)
and also as r
DS
and r
ds
. In
either case, however, it is measured, for JFETs, by tying the
gates to the source, setting all terminals equal to 0 Vdc, and
applying an ac voltage from drain to source (see Figure 20).
The magnitude of the ac voltage should be kept low so that
there will be no pinchoff in the channel. Insulated-gate FETs
may be measured with dc gate bias in the enhancement
mode.
Channel resistance describes the bulk resistance of
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Figure 20. Circuit for Measuring JFET
Channel Resistance
APPLICATIONS
Device Selection
Obviously, different applications call for special emphasis
on specific characteristics so that a simple figure of merit
that compares devices for all potential uses would be hard
to formulate. Nevertheless, an attempt to pinpoint the
characteristics that are most significant for various
applications has been made* to permit a rapid, first-order
evaluation of competitive devices.
The most important single FET parameter, one that
applies for any amplifier application, is y
fs
. This parameter,
or one of its many variations, is specified on most data
sheets, yet some evaluation is required to come up with a
reasonable comparison. For example, in the table of
electrical characteristics on most JFET data sheets, y
fs
is
specified at I
DSS
(V
GS
= 0) where, for JFETs devices, y
fs
is maximum. This is illustrated in Figure 14, where typical
variations of y
fs
as a function of I
D
are plotted. For some
small-signal applications, the I
DSS
(V
GS
= 0) point can
actually be used as a dc operating point because
small-signal excursions into the forward bias region will not
actually cause the gate-source junction to become
forward-biased. However, in most practical uses, some bias
is necessary to allow for the anticipated signal swing; and
it must be recognized the y
fs
goes down as the bias is
increased.
It is seen, also, that maximum y
fs
increases as I
DSS
increases so that, where maximum y
fs
is important, a device
with a high I
DSS
specification is normally desirable.
On the other hand, where power dissipation is a factor
to be considered, the figure of merit y
fs
/V
GS(off)
I
DSS
has
been proposed. This term factors in not only I
DSS
, which
should be low if power dissipation is to be low, but also
V
GS(off)
, which indicates maximum input voltage swing.
Since the signal peaks are represented by V
GS
= V
GS(off)
and V
GS
= 0, the lower V
GS(off)
, the higher the figure of
merit. And, for amplifier applications requiring a large signal
swing, V
(BR)GSS
/V
GS(off)
(assuming that V
GS(off)
is the
“pinch-off” voltage) is a satisfactory merit figure because it
indicates the ratio of maximum and minimum drain voltages.
* Christiansen, Donald, “Semiconductors: The New Figures of Merit,”
EEE, October, 1965.
F
Freescale Semiconductor, Inc.
Go to: www.freescale.com
n
.
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