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參數(shù)資料
| 型號： | AN2104 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | Using Background Debug Mode for the M68HC12 Family |
| 中文描述： | 使用的M68HC12家庭背景調(diào)試模式 |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 414K |
| 代理商： | AN2104 |
Application Note
Theory of Operation
AN2104
7
BDMACT — Background Mode Active Status Bit
0 = BDM not active
1 = BDM active and waiting for serial commands
ENTAG — Instruction Tagging Enable Bit
Set by the TAGGO instruction and cleared when BDM is entered
0 = Tagging not enabled or BDM active
1 = Tagging active (BDM cannot process serial commands while
tagging is active.)
SDV — Shifter Data Valid Bit
Shows that valid data is in the serial interface shift register. Used by
firmware-based instructions.
0 = No valid data
1 = Valid data
TRACE
Asserted by the TRACE1 instruction
The second register of interest is the BDM CCR holding register. This
register contains the value of the CPU’s condition code register (CCR)
from the user’s program upon entering the BDM. See
Figure 4
.
Operation
of Active BDM
Here is a brief description of what transpires when going into the active
BDM:
When the CPU gets the command to go into the BDM, the user’s
return address is stored in a temporary register.
Next, the BDM ROM is turned on and the CPU fetches a vector
that points to the beginning of the BDM firmware program.
Address: $FF06
Bit 7
6
5
4
3
2
1
Bit 0
Read:
CCR7
CCR6
CCR5
CCR4
CCR3
CCR2
CCR1
CCR0
Write:
Reset:
0
0
0
0
0
0
0
0
Figure 4. BDM CCR Holding Register (CCRSAV)
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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