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參數(shù)資料
| 型號： | AN2104 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | Using Background Debug Mode for the M68HC12 Family |
| 中文描述： | 使用的M68HC12家庭背景調(diào)試模式 |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 414K |
| 代理商： | AN2104 |
Application Note
AN2104
6
BDM Registers
Seven BDM registers are mapped into addresses $FF00–$FF06. See
Table 3
.
NOTE:
Remember that the BDM firmware ROM and registers contain different
data than the normal memory mapped locations for these addresses.
Only two registers are discussed here:
BDM status register (STATUS)
BDM CCR (condition code register) holding register (CCRSAV)
The BDM status register can be read at any time, but must not be written
to during BDM operation. See
Figure 3
for a description of the bits.
This register can be read or written by BDM commands or firmware.
ENBDM — Enable BDM Bit (permit active background debug mode)
0 = BDM cannot be made active (hardware commands still
allowed).
1 = BDM can be made active to allow firmware commands.
Table 3. BDM Registers
Address
Register
Mnemonic
$FF00
BDM instruction register
INSTRUCTION
$FF01
BDM status register
STATUS
$FF02–$FF03
BDM shift register
SHIFTER
$FF04–$FF05
BDM address register
ADDRESS
$FF06
BDM CCR holding register
CCRSAV
Address: $FF01
Bit 7
6
5
4
3
2
1
Bit 0
Read:
ENBDM
EDMACT
ENTAG
SDV
TRACE
0
0
0
Write:
Reset:
0
0
0
0
0
0
0
0
Single-Chip
Peripheral:
1
0
0
0
0
0
0
0
Figure 3. BDM Status Register (STATUS)
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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