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參數(shù)資料
| 型號(hào)： | AN207 |
| 廠商： | Vishay Intertechnology,Inc. |
| 英文描述： | 12-ns DG611 Switch Family Combines Benefits of CMOS and DMOS Technologies |
| 中文描述： | 12納秒DG611開(kāi)關(guān)系列組合的優(yōu)點(diǎn)CMOS和DMOS技術(shù) |
| 文件頁(yè)數(shù)： | 5/12頁(yè) |
| 文件大?。?/td> | 149K |
| 代理商： | AN207 |
AN207
Vishay Siliconix
Document Number: 70605
03-Aug-99
www.vishay.com FaxBack 408-970-5600
6-5
FIGURE 7.
Typical r
DS(on)
Characteristics
600
500
400
100
0
0
2
200
300
4
6
8
10
12
14
16
18
20
+5 V
V
L
V–
GND
V
S
V+
I
SD
r
)
V
S
– Source Voltage (V)
a) V+ = 5 V
b) V+ = 12 V
c) V+ = 12 V, I
SD
= 10 mA
a)
b)
c)
IN
V–
D
S
V+
V–
V+
FIGURE 8.
ESD Protection Diodes are Located at all
Control and Switch Pins
Figure 7 illustrates typical on-resistance curves. Curve (a)
represents single 5-V operation. Assuming a maximum
acceptable r
DS(on)
value of 200
, the usable analog signal
range goes from 0 V to slightly over 2 V. Curve (b) shows
operation with V+ = 12 V. Now the usable signal range has
increased to 8 V. If you want to operate in the flat,
low-resistance part of the curve, you may want to limit your
analog signal to no more than 6 V. Curve (c) was generated
using a –10-mA I
D
current. Note that when V
S
= 12 V, it still
shows an r
DS(on)
= 480
. To sink 10 mA, V
D
has gone down
to 7.2 V, and this creates a partial channel enhancement.
ESDS (ESD Sensitivity)
By incorporating a CMOS driver in front of the DMOS FET,
direct access to the DMOS gate has been eliminated. By itself,
this goes a long way to reduce ESD sensitivity. Additional ESD
protection diodes have been added to the source and drain
pins. Nevertheless, to maintain high speed, a compromise
between ESD protection, speed, on-resistance, and
on-capacitance had to be reached. This means that the
protection diodes are relatively small and protect only up to
about 500 V. To prevent damage from high-energy
electrostatic fields, anti-static handling precautions must be
observed at all times.
Applications
Following is a collection of practical application hints and
design ideas intended to help you design with the DG61X
family.
High-Speed 8-Channel Analog Multiplexer
If you are designing a high-speed data acquisition system,
then you will need a very fast analog multiplexer. A fast
multiplexer like the DG408 specifies a typical transition time of
160 ns. By using the DG611 to make the multiplexer shown in
Figure 9, you will achieve transition times in the 30-ns range,
a sixfold speed improvement. This added speed will allow you
to achieve sampling rates in excess of 3 MHz, as
demonstrated below.
For an 8-channel multiplexer the maximum sampling rate is
given by:
f
S
1
8
(t
SETTLING
t
TRANS
)
(1)
where t
SETTLING
= N
r
DS(on)
C
(on)
(2)
for an accuracy of 0.01% (12 bits) N = 9.
For small signals, let us assume that typical r
DS(on)
= 18
The output node capacitance is given by:
C
(on)
= 1 C
D(on)
+ 7 C
D(off)
= 10 pF + 7
2 pF = 24 pF
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