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參數(shù)資料
| 型號(hào)： | AN101 |
| 廠商： | Vishay Intertechnology,Inc. |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:3; Series:MS27508; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:8; Circular Contact Gender:Pin; Circular Shell Style:Box Mount Receptacle; Insert Arrangement:8-98 RoHS Compliant: No |
| 中文描述： | MOSFET的 |
| 文件頁(yè)數(shù)： | 3/5頁(yè) |
| 文件大?。?/td> | 44K |
| 代理商： | AN101 |
AN101
Siliconix
10-Mar-97
3
In Figure 4, consider the case where V
DS
= 0 and where
a negative voltage V
GS
is applied to the gate. Again, a
depletion layer has built up. If a small value of V
DS
were
now applied, this depletion layer would limit the resultant
channel current to a value lower than would be the case
for V
GS
= 0. In fact, at a value of V
GS
>
V
P
the channel
current would be almost entirely cut off. This cutoff volt-
age is referred to as the gate cutoff voltage, and may be
expressed by the symbol V
P
or by V
GS(off)
. V
P
has been
widely used in the past, but V
GS(off)
is now more com-
monly accepted since it eliminates the ambiguity be-
tween gate cut-off and drain pinch-off.
P
S
D
N
G
Depletion
Layer
P
V
GS
Figure 4.
N-Channel FET Showing Depletion Due to
Gate-Source Voltage and V
DS
= 0
The mechanisms of Figures 3 and 4 react together to pro-
vide the family of output characteristics shown in Figure
5a. The area below the pinch-off voltage locus is known
as the ohmic region: the area above pinch-off is current
saturation region. JFETs operating in the current satura-
tion region make excellent amplifiers. Note that in the
ohmic region both V
GS
and V
DS
control the channel cur-
rent, while in the current saturation region V
DS
has little
effect and V
GS
essentially controls I
D
.
Figure 5b relates the curves in Figure 5a to the actual cir-
cuit arrangement, and shows the number of meters which
may be connected to display the conditions relevant to
any combination of V
DS
and V
GS
. Note that the direction
of the arrow at the gate gives the direction of current flow
for the forward-bias condition of the junction. In practice,
however, it is always reverse-biased.
The p-channel JFET works in precisely the same way as
the n-channel JFET. In manufacture, the planar process is
essentially reversed, with the acceptor impurity diffused
first onto n-type silicon, and the donor impurity diffused
later to form a second n-type region and leave a p-type
channel. In the p-channel JFET, the channel current is due
sequently, all the applied polarities are reversed, along
with their directions and the direction of current flow.
In summary, a junction FET consists essentially of a chan-
nel of semiconductor material along which a current may
flow whose magnitude is a function of two voltages, V
DS
and V
GS
. When V
DS
is greater than V
P
, the channel cur-
rent is controlled largely by V
GS
alone, because V
GS
is ap-
plied to a reverse-biased junction. The resulting gate cur-
rent is extremely small.
0
–
+
+
–
V
DS
D
S
G
V
GS
= 0
V
DS
V
P
V
DS
=
V
P
–
V
GS
I
D
I
D
I
DSS
V
GS
Figure 5.
5a)
Family of Output Characteristics
for N-Channel FET
5b)
Circuit Arrangement for N-Channel FET
V
GS(off)
V
GS
= –V
I
D
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