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參數(shù)資料
| 型號： | AN10145 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Bi-directional low voltage translators |
| 中文描述： | 雙向低電壓轉(zhuǎn)換器 |
| 文件頁數(shù)： | 5/24頁 |
| 文件大?。?/td> | 325K |
| 代理商： | AN10145 |
5
Cross-Bar Technology (CBT) Like Behavior
The large NMOS pass transistors used in the GTL-TVC devices are very similar to the large NMOS pass transistors used
in CBT devices. However unlike the CBT devices that use internal drivers to control the gate of the NMOS pass
transistor, the gate pin of the GTL-TVC devices is directly connected to the gate of each transistor. In principle the
GTL-TVC devices can be used like CBT devices except that the gate input capacitance is much larger than a normal
CBT device. When using the GTL-TVC devices as CBT devices, the gate pin (GREF) is driven by external logic to the
power supply, to enable it, or to ground to disable it, and the SREF and DREF pins can be used as an additional channel
as shown in Figure 3.
Figure 3. Cross Bar Technology like Application
Note:
If a 5 V to 3.3 V translation is wanted, best results are achieved using the bias circuit of the GTL-TVC with the
SREF at 3.3 V. Additionally, when used as a CBT function with the gate at V
DD
and the input at V
DD,
the maximum pass
voltage will be ~ V
DD
– 1 V because the output is shifted down by a threshold compared to the gate voltage.
Features
The GTL-TVC family has several features that benefit a system designer when designing an interface between devices
with different I/O voltage levels.
Device Construction
– The GTL-TVC devices are of a very simple design. The only required connections are GND,
gate of the reference transistor (GREF), drain of the reference transistor (DREF) and source of the reference transistor
(SREF) and then any of the Dn/Sn I/O pairs needed for voltage level translations.
Any transistor Dn or Sn I/O pair can be used as the source or drain of the reference transistor (SREF or DREF). This
makes it easier to route signals to and from the device.
All the transistors are on one die, which is manufactured with very tight process control. This provides a very low
spread of V
O
relative to SREF or DREF.
It is easy to change the SREF voltage allowing the system designer an easy migration path to even lower voltages
(e.g. 1.5 V or 1.2 V).
Dn /Sn I/O pairs are matched on either side of the devices (e.g., flow through pinout) which offers easy trace
routing.
No Active Control Logic
– As shown in Figure 4, the GTL-TVC is a passive device and there is no active control logic.
This means there is no supply power (V
DD
) required for device operation.
Figure 4. GTL20XX Logic Diagram
GND
SREF
S1
S2
GREF
DREF
D1
D2
GTL2002
Chipset I/O
Chip set
V
DD
V
DD
5 V
Control
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