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參數(shù)資料
| 型號(hào)： | AN-5025 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Applications Using the GTLP10B320 |
| 中文描述： | 應(yīng)用程序使用GTLP10B320 |
| 文件頁(yè)數(shù)： | 2/3頁(yè) |
| 文件大?。?/td> | 377K |
| 代理商： | AN-5025 |
www.fairchildsemi.com
2
A
Operation and Specifications
The general operation of the GTLP10B320 is similar to
other GTLP devices designed to the JEDEC standard
JESD8-3, with features such as:
Open drain technology on GTLP, capable of sinking
+
50mA
Voltage swing of
<
1V, low power consumption and EMI
User ability to adjust variables (R
TERM
, V
TT
, and V
REF
)
to optimize backplane characteristics
Bushold on the TTL A Port, eliminating need for pull-up
resistors on TTL side
Incident wave switching, enabling higher throughput
Outputs are high impedance during power up/down for
live insertion
Modes of operation include latched/transparent and reg-
istered
Figure 2 illustrates the five basic modes possible for the
GTLP10B320. Register and latch options are available for
each mode using the latch enable pin LECLK and the
directional select pins SAB and SBC. For additional details
refer to the datasheet.
The GTLP10B320 is designed for optimal performance into
a 10pF lumped load. This better characterizes its perfor-
mance in a true distributed load backplane, which is the
most common application. AC characteristics are specified
with both a 10pF lumped load and the standard 30pF
lumped load in the datasheet. This provides the designer
with more realistic representation of how the device will
perform in a system as well as the ability to make compari-
sons to other GTLP devices.
Summary
The GTLP10B320 is an important innovation in backplane
drivers that allows for split TTL inputs and outputs as well
as an internal feedback path. These two features can add
to the performance and/or diagnostic capabilities of a sys-
tem.
FIGURE 2. GTLP10B320 Operation Modes
(1-Bit Shown)
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