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| 型號(hào)： | AN-5061 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Layout Guidelines |
| 中文描述： | 布局指南 |
| 文件頁(yè)數(shù)： | 1/4頁(yè) |
| 文件大?。?/td> | 138K |
| 代理商： | AN-5061 |
www.fairchildsemi.com
2004 Fairchild Semiconductor Corporation
Rev. 1.0.3 4/30/07
www.fairchildsemi.com
AN-5061
Layout Guidelines
Summary
Fairchild’s μSerDes devices can be used to minimize the
cost and complexity associated with the design of parallel
interface connections. Since these devices are capable of
reducing a parallel data path to a serialized differential pair,
the number of signals needed across the interface media is
diminished. This reduction in signal count translates to a
cost savings through decreased layer counts and size. This
guide addresses some questions that might arise with the
design and layout of μSerDes devices.
The serial I/O information is transmitted at a high serial
rate. Care must be taken implementing this serial I/O flex
cable. The following best practices should be used when
developing the flex cabling:
All four differential serial wires should be the same
length
No noisy signals over or near differential serial wires
One ground plane or ground wire over the differential
serial wires
No test points on the differential serial wires
Provide a separate RF ground for phones that have a
metal housing
Differential serial wires should be a minimum of 2cm
from antenna
Impedance measured from customer flex:
-
Best: 80-120ohm
-
Typical: 70-130ohm
Differential Pair Design
The μSerDes devices have been designed so that a 180-
degree rotation of either device results in a straight-forward
alignment of the serial clock and data lines. This
arrangement is intended to make the layout of the
differential trace routes as clean as possible. Typical bi-
directional mode connections are shown in Figure 1.
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MLP
Master
M/S
PAR/SPI
/RES
DS+
DS-
VDDA
VDDS
CKS-
CKS+
CKSEL(H)
MLP
Slave
CKSEL(H)
(DS+)
(DS-)
VDDS
VDDA
(CKS-)
(CKS+)
/RES
PAR/SPI
M/S
Figure 1.
FIN324C Serial Port Alignment
The positive and negative signals of the differential pair
must have the same length. The difference in trace length
should not exceed 20mils, approximately 3ps in skew.
When designing with μSerDes devices, it is necessary to
keep the lengths of the serial data pairs equivalent to the
lengths of the serial clock pairs. The amount of mismatch
allowed is based on the frequency of operation. The lower
the frequency, the greater the allowable mismatch.
Do not route signals (differential or parallel) over any type
of plane split, which results in a significant impedance
discontinuity and increased loop area of return currents.
Differential pairs should be routed on the same layer and the
number of vias on the differential lines should be
minimized.
It is not necessary to round corners of a differential trace
route: 45-degree corners are sufficient.
The main consideration with differential pairs should be
electrical balance. Any discontinuity (ex. vias, pads, stubs,
layer transitions, and crosstalk) introduced to one side of the
differential pair should be introduced equally to the other
side. Minimize discontinuities as much as possible.
Whether or not the differential traces are tightly or loosely
coupled is application specific. Priority should be given to
the matching of lengths between the positive and negative
pairs over the trace to trace configuration.
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