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| 型號： | AN-1192 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | broad portfolio of monolithic power integrated circuits covering power levels |
| 中文描述： | 豐富的產品組合覆蓋功率級別單片功率集成電路 |
| 文件頁數： | 6/21頁 |
| 文件大?。?/td> | 548K |
| 代理商： | AN-1192 |
5.0 BR100—100W Bridge Circuit
(Continued)
5.2 SCHEMATICS
5.2.1 Bridged Amplifier Schematic
5.2.2 Electrical Design Notes
The following electrical design notes will aid in making the
bridged amplifier design go more smoothly while also help-
ing to achieve the highest level of performance.
The input impedance of the inverting amplifier is essen-
tially resistor, R
i
. The value of this resistance affects the
gain setting of the amplifier as well as the low frequency
rolloff in conjunction with C
i
. There is a tradeoff between
having a low frequency rolloff, a high input impedance
and a small capacitor size and value. It is critical to have
a flat band response down to 20Hz while it is equally
important to have a high enough input impedance so that
heavy loading does not occur from the preamp stage.
Using large valued low-cost capacitors implies the use of
leaky electrolytics which affect the output offset voltage.
Electrolytic capacitors are also less linear than other
premium caps and should not be used in the signal path
when not necessary. This tradeoff issue is the toughest
portion of the design. The amplifier gain setting is just as
one would expect for an inverting op amp. Of course, the
input impedance issue can be quickly resolved by using a
voltage follower as an input buffer, but it was omitted from
this design to minimize cost and simplify the design. The
values provided in the bridged schematic are at a good
tradeoff point. There is sufficient input impedance for
practically all audio op amps, the closed-loop gain setting
is 11 for each amplifier, (gain of 22 overall) while the
capacitor value of 4.7μF sets the low frequency 3dB
rolloff at about 7Hz.
The non-inverting input resistance, R
, is used to create a
voltage drop at the non-inverting terminal to offset the
voltage at the inverting input terminal due to the input
bias current flowing from the output to the inverting input.
Generally, the value of this resistor equals the value of
the feedback resistor so that the output offset voltage will
be minimized close to zero. However, if this value is too
large, noise can easily be picked up which will be ampli-
fied and seriously affect the THD+N performance. If the
resistor is eliminated and the terminal is grounded, the
THD+N performance will be much better, but it will not
necessarily be optimized. By connecting the non-
inverting input directly to a ground reference, any noise
on that ground will be directly injected into the amplifier,
amplified and thus will also affect the THD+N perfor-
mance. The best solution is to use a value of resistance
that is not too large that it picks up stray noise and not too
small as to be affected by ground noise fluctuations. The
value used in the previous plots was a 3.32k
resistor. It
should be noted that this is not necessarily the optimized
value and can change with varying circuit layouts.
Low leakage signal path capacitors should be used
where possible to reduce output offset voltages. This is
not too big of an issue since each gain stage has only
unity gain at DC. This is another reason why 1% resistor
tolerances are not necessarily required. To obtain the
highest quality amplifier, polypropylene capacitors should
be employed in the signal path and supply bypassing.
20015103
FIGURE 3. Bridged Amplifier Schematic
A
www.national.com
6
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