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| 型號： | AN-06 |
| 英文描述： | SY89429A Frequency Synthesis |
| 中文描述： | SY89429A頻率合成 |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 189K |
| 代理商： | AN-06 |
2
APPLICATION NOTE
AN-06
Micrel
the total supply voltage. In the case of a +3.3V system, a –
2V supply is needed to provide the required +5V across
V
CC
and V
EE
terminals. Specifically, all V
CC
pins including
V
CC
_
OUT
are connected to +3.3V supply. All ground pins
are connected to –2V supply. This configuration eliminates
the need for a +5V supply if there is a –2V supply already
in the system. However, it also creates some interesting
interface problems.
Since the most positive power supply is +3.3V, the XTAL1,
XTAL2, FOUT and /FOUT interface to +3.3V PECL signal.
If TTL interface is required, SY100ELT22L may be used at
the XTAL1 and XTAL2 pins for translating the TTL signal to
a +3.3V PECL signal. The SY100ELT23L can be used at
FOUT and /FOUT pins for translating the +3.3V PECL signal
to a TTL signal. Both SY100ELT22L and SY100ELT23L
require only a single +3.3V power supply. Figure 5 shows a
split supply design with TTL interface for XTAL1, XTAL2,
FOUT and /FOUT.
Interfacing to all other inputs is trickier. As mentioned
before, these inputs have internal pull up resistors.
Therefore, any input can be left open and open inputs are
logical “1” state. Although inputs are allowed to be open, it
is recommended that open inputs be connected to a power
supply line. These inputs can be connected to V
CC
lines
(+3.3V for a logical “1”) or V
EE
lines (–2V for a logical “0”)
directly or through series resistors. These inputs can also
be driven by TTL or PECL signals with proper signal
translators. Figure 6 shows the translation for a normal TTL
signal. Figure 7 shows the translation for a +3.3V PECL
signal.
True ECL Design
The SY89429A is designed for TTL/PECL systems. It
can be designed into a pure ECL environment easily.
Connect all V
CC
pins to ground and all GND pins to –4.5V
(or –5.2V) power supply line. With this operating condition,
XTAL1, XTAL2, FOUT and /FOUT interfaces directly with
normal 100K ECL signals. All other inputs have internal pull
up resistors. Therefore, any input can be left open and
open inputs are logical “1” state. Although inputs are allowed
to be open, it is recommended that open inputs be connected
to a power supply line. These inputs can be connected to
ground lines (0 volt for a logical “1”) or negative power
supply lines (–4.5V or –5.2V for a logical “0”) directly or
through series resistors. These inputs can interface to normal
ECL signals with SY100ELT23 for signal translation. Figure
8 shows the schematic with signal translations.
Advanced Frequency Control Applications
The primary function of this product is to synthesize clock
frequencies from 25MHz to 400MHz in 1MHz steps with a
16.00MHz crystal. However, there are many other
applications that are not so obvious. Even though SY89429A
is said to be able to generate frequencies between 25MHz
to 400MHz in 1MHz steps with a 16MHz crystal, output
Input Reference Frequency And
On-Chip Crystal Oscillator
The SY89429A is designed based on input reference
frequency of 16MHz and phase detector frequency of
2MHz. A 16MHz differential PECL clock source can be
used to drive the XTAL1 and XTAL2 pins directly. An
alternative to a PECL clock source is to utilize the on-
chip crystal oscillator. This oscillator requires only an
off-chip 16MHz reference crystal connected between
XTAL1 and XTAL2 pins. A 5.6k
resistor connected in
parallel with the crystal is recommended. For using other
input reference frequencies, refer to section titled
“
Advance Frequency Control Applications
.” Using
16MHz reference frequency, the output frequency can
be programmed from 25MHz to 400MHz in 1MHz steps.
Due to variability of the device, the crystal and the printed
circuit board, connecting a fixed value capacitor in the 5-
20pF range in series with the crystal should provide
frequency control to 100ppm. Figure 3a shows the
recommended crystal oscillator circuit. A variable
capacitor can be used instead of the fixed capacitor to
achieve frequency control better than 100ppm with
manual adjustment. Varactors can also be included for
using SY89429A as a voltage controlled oscillator. For
more frequency control applications, please refer to the
sections titled “
Advanced frequency control
applications
” and “
Voltage controlled crystal oscillator
applications
.” For interfacing to TTL/CMOS clock
sources, SY100ELT22 may be used to translate a TTL/
CMOS signal to PECL signal.
Filter Design
The filter for any Phase Locked Loop (PPL) based device
deserves special attention. SY89429A provides filter pins
for an external filter. A simple three-components passive
filter is recommended for achieving ultra low jitter. Figure
3b shows the recommended three-components passive
filter. Due to the differential design, the filter is connected
between LOOP_FILTER and LOOP_REF pins. With this
configuration, extremely high supply noise rejection is
achieved. It is important that the filter circuit and filter pins
be isolated from any non-common mode coupling and placed
in the V
CC
plane.
Generating High Speed TTL Clock Signals
A high speed PECL-to-TTL translator such as SY10/
100ELT23 or SY10/100ELT23L (for +3.3V) may be used to
generate high speed TTL compatible signals. High speed
PECL to TTL translating Clock Drivers such as SY10/
100841/842 or SY10/100641/646 may be added if multiple
copies of such clocks are desired. These translators are
capable of driving 50pF loads up to 160MHz.
Split Supply Design
In systems where +5V are not available, a split supply
design may be the solution. Split supply generally refers to
using a positive supply and a negative supply to make up
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