
10
AMMP-6640 Bias and Usage
The AMMP-6640 attenuator is driven by voltage ramps
placed on Vseries and Vshunt control pins. Operation in
this mode requires voltages between 0 to 1.5 volts for Vse
and 0 to 1.5 volts for Vsh. The recommended DC control
voltage range is Vse = 0 to 1.2 volts and Vsh = 0 to 1.2
volts. A simplified schematic for the AMMP-6640 is shown
in Figure 17.
In the minimum attenuation state, the series FETs are
fully biased at 1.2 volts and the shunt FETs are in the full
“off” state at 0 volts. Inversely, for a maximum attenuation
state, the series FETs are “off” at 0 volts bias and the shunt
FETs are fully on at 1.2 volts. Achieving attenuation levels
in-between these two states requires voltage levels similar
to those in Table 4. Applying voltage to the shunt FETs sets
the source to drain resistance and establishes the main
attenuation level. The match is optimized by the amount
of bias applied to the series FETs. The match will determine
how flat the attenuation level is across a broadband
operational range.
Figure 17. AMMP-6640 Schematic
Table 4. AMMP-6640 Typical Control Voltages
Attenuation (dB)
Vseries (V)
Vshunt (V)
0
1.2
0
2
0.440
0.325
4
0.435
0.383
6
0.430
0.416
8
0.420
0.440
10
0.410
0.465
12
0.400
0.480
14
0.385
0.505
16
0.375
0.535
18
0.360
0.575
20
0.350
0.650
22
0.346
0.845
max
0
1.2
Figure 18. Suggested Lead-Free Reflow Profile for SnAgCu Solder Paste
Manual Assembly
x Follow ESD precautions while handling packages.
x Handling should be along the edges with tweezers.
x Recommended attachment is conductive solder paste.
Please see recommended solder reflow profile. Neither
Conductive epoxy or hand soldering is recommended.
x Apply solder paste using a stencil printer or dot place-
ment. The volume of solder paste will be dependent
on PCB and component layout and should be con-
trolled to ensure consistent mechanical and electrical
performance.
x Follow solder paste and vendor’s recommendations
when developing a solder reflow profile. A standard
profile will have a steady ramp up from room temper-
ature to the pre-heat temp. to avoid damage due to
thermal shock.
x Packages have been qualified to withstand a peak tem-
perature of 260°C for 20 seconds. Verify that the profile
will not expose device beyond these limits.
A properly designed solder screen or stencil is required
to ensure optimum amount of solder paste is deposited
onto the PCB pads. The recommended stencil layout is
shown in Figure 19b. The stencil has a solder paste depo-
sition opening approximately 70% to 90% of the PCB pad.
Reducing stencil opening can potentially generate more
voids underneath. On the other hand, stencil openings
larger than 100% will lead to excessive solder paste smear
or bridging across the I/O pads. Considering the fact that
solder paste thickness will directly affect the quality of
the solder joint, a good choice is to use a laser cut stencil
composed of 0.127mm (5 mils) thick stainless steel which
is capable of producing the required fine stencil outline.
The most commonly used solder reflow method is accom-
plished in a belt furnace using convection heat transfer. The
suggested reflow profile for automated reflow processes is
shown in Figure 18.This profile is designed to ensure reliable
finished joints. However, the profile indicated in Figure 1 will
vary among different solder pastes from different manu-
facturers and is shown here for reference only.
0
50
100
150
200
250
300
0
50
100
150
200
250
300
Seconds
Temp
(°C)
Peak = 250 ± 5°C
Ramp 1
Preheat Ramp 2
Reow
Melting point = 218°C
Cooling
NC
VSH
VSE
NC
RFOUT
RFIN
1
2
3
7
6
5
8
4
Package
Base
Ground
0.1
μF
0.1
μF