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參數(shù)資料
| 型號： | AMIS39101AGA |
| 英文描述： | Octal High-Side Driver with Protection |
| 中文描述： | 八路高端驅動器的保護 |
| 文件頁數(shù)： | 9/15頁 |
| 文件大小： | 413K |
| 代理商： | AMIS39101AGA |
AMIS-39101:
Octal High-Side Driver with Protection
Data Sheet
8.6.3. Ground Loss
Due to its design, the AMIS-39101 is protected for withstanding module ground loss and driver output shorted to ground at the same
time.
8.6.4. Power Loss
Table 10: Power Loss
VDDN
0
0
VS
0
1
Possible Case
System stopped
Start case or sleeping mode with missing VDDN
Action
Nothing
Eight switches in the off-state
Power down consumption on VS
Eight switches in the off-state
Normal consumption on VDDN
Nominal functionality
1
0
Missing VS supply
VDDN normally present
System functional
1
1
8.7 SPI interface
The serial peripheral interface (SPI) is used to allow an external microcontroller (MCU) to communicate with the device. The
AMIS-39101 acts always as a slave and it can’t initiate any transmission.
8.7.1. SPI Transfer Format and Pin Signals
The SPI block diagram and timing characteristics are shown in Figure 6 and Figure 7.
During an SPI transfer, data is simultaneously sent to and received from the device. A serial clock line (CLK) synchronizes shifting and
sampling of the information on the two serial data lines (DIN and DOUT). DOUT signal is the output from the AMIS-39101 to the
external MCU and DIN signal is the input from the MCU to the AMIS-39101. The WR-pin selects the AMIS-39101 for communication
and can also be used as a chip select (CS) in a multiple-slave system. The WR-pin is active low. If AMIS-39101 is not selected, DOUT
is in high impedance state and it does not interfere with SPI bus activities. Since AMIS-39101 always shifts data out on the rising edge
and samples the input data also on the rising edge of the CLK signal, the MCU SPI port must be configured to match this operation.
SPI clock idles high between the transferred bytes.
The diagram in Figure 7 represents the SPI timing diagram for 8-bit communication.
Communication starts with a falling edge on the WR-pin which latches the status of the diagnostic register into the SPI output register.
Subsequently, the CMD_x bits – representing the newly requested driver status – are shifted into the input register and simultaneously,
the DIAG_x bits – representing the actual output status – are shifted out. The bits are shifted with x=1 first and ending with x=8. At the
rising edge of the WR-pin, the data in the input register is latched into the command register and all drivers are simultaneously
switching to the newly requested status. SPI communication is ended.
In case the SPI master does only support 16-bit communication, then the master must first send 8 clock pulses with dummy DIN data
and ignoring the DOUT data. For the next 8 clock pulses the above description can be applied.
The required timing for serial to peripheral interface is shown in Table 11.
9
AMI Semiconductor
– November 06 - M-20638-001
www.amis.com
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