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參數(shù)資料
| 型號(hào)： | AMIS39101AGA |
| 英文描述： | Octal High-Side Driver with Protection |
| 中文描述： | 八路高端驅(qū)動(dòng)器的保護(hù) |
| 文件頁(yè)數(shù)： | 10/15頁(yè) |
| 文件大?。?/td> | 413K |
| 代理商： | AMIS39101AGA |
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AMIS-39101:
Octal High-Side Driver with Protection
Data Sheet
Table 11: Digital Characteristics
Symbol
T_CLK
T_DATA_ready
Description
Maximum applied clock frequency on CLK input
Time between falling edge on WR and first bit of data ready on
DOUT output
(driver going from HZ state to output of first diagnostic bit)
First clock edge from falling edge on WR
Setup time on DIN
Hold time on DIN
Time between rising edge on CLK and next bit ready on DOUT (capa
on DOUT is 30pF max.)
Time between last CLK edge and WR rising edge
Rise and fall time of all applied signals
(maximum loading capacitance is 30pF)
Time between two rising edge on WR
(repetition of the same command)
Min.
Max.
500
2
Unit
kHz
μs
T_CLK_first
T_setup
T_hold
(1)
T_DATA_next
3
20
20
μs
ns
ns
ns
100
T_SPI_END
T_risefall
1
5
μs
ns
20
T_WR
300
μs
Note:
(1)
Guaranteed by design
Normal mode verification:
The
command
is the set of eight bits loaded via SPI, which drives the eight HS drivers on or off.
The
command
is activated with rising edge on WR pin.
Table 12: Digital Characteristics
Symbol
Description
T_command_L_max.
(1)
Minimum time between two opposite commands for inductive
loads and maximum HS driver current of 275mA
T_command_R
(1)
Minimum time between two opposite commands for resistive
loads and maximum HS driver current of 350mA
T_PDB_recov
percent of VS-1V on all HS driver outputs. (all drivers are
activated, pure resistive load 35mA on all outputs)
Note:
(1)
Guaranteed by design
Min.
Max.
Unit
1
s
2
ms
The time between the rising edge on the PDB input and 90
1
ms
10
AMI Semiconductor
– November 06 - M-20638-001
www.amis.com
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