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參數(shù)資料
| 型號(hào)： | AMIS-720658 |
| 英文描述： | Contact Image Sensor |
| 中文描述： | 接觸式圖像傳感器 |
| 文件頁數(shù)： | 7/15頁 |
| 文件大小： | 560K |
| 代理商： | AMIS-720658 |
AMIS-720658: Contact Image Sensor
Data Sheet
6.0 Recommended Operating Conditions
Table 3 lists the recommended operating conditions at 25
°
C.
Table 3: Recommended Operating Conditions at 25
°
C
Parameter
Power supply
Clock input voltage high level
(1)
Clock input voltage low level
(1)
Reference voltage
Clock frequency
(3)
Pixel rate
(4)
Integration time (line scan rate)
(5)
First die
Subsequent die
Clock pulse duty cycle
(6)
Resistive load on Vout
Capacitive load on Vout
Notes:
1.
Applies to all clocks; GBST, SI and CLK.
2.
The dark level is set by the voltage on VREF and which must be applied externally, to a voltage of 1.2V for optimal module operation.
3.
Although the device will operate with a pixel rate of less than 500 kHz, it is recommended that the device be operated above 500 kHz to maintain performance
characteristics. Operating below 500 kHz may result in leakage current degradation.
4.
One pixel is clocked out for every clock cycle.
5.
Tint is the integration time of a single sensor and is the time between two start pulses. The minimum integration time is the time it takes to clock out 82 inactive pixels
and 344 active pixels for the 600dpi mode, or 82 inactive pixels and 172 active pixels for the 300dpi mode, at a given frequency.
However, if several sensors are cascaded together in a module then the minimum integration time for the 600dpi mode is the time it takes to clock out 82 inactive pixels
and 344 active pixels from the first sensor and 344 pixels from each of all subsequent sensors, at a given frequency.
Similarly, for cascaded sensors in the 300dpi mode, the minimum integration time is the time it take to clock out 82 inactive pixels and 172 active pixels from the first
sensor and 172 pixels from each of all subsequent sensors, at a given frequency.
6.
The clock duty cycle is defined as the ratio of the positive duration of the clock to its period.
Symbol
Vdd
Vih
Vil
VREF
Min.
3.1
2.8
1.1
0.5
0.5
107
86
5
Typ.
3.3
1.2
3.0
3.0
Max.
3.5
0.5
1.3
4.0
4.0
Units
V
V
V
V
MHz
MHz
μ
s
μ
s / die
%
K
pF
Tint
50
50
7.0 Absolute Maximum Ratings
Table 4: Absolute Maximum Ratings
Parameter
Power supply voltage (Vdd)
Clock input voltage high level (Vih)
(1)
Clock input voltage low level (Vil)
(1)
Symbols
Vdd
Vih
Max.
8
Vdd + 0.3
Units
V
V
Vil
-0.3
V
Operating temperature
-10 to +50
°C
Operating humidity
+10 to +85
RH%
Storage temperature
Storage humidity
Note:
1.
Applies to all clocks.
-25 to +75
+10 to +90
°C
RH%
7
AMI Semiconductor
– Jul 06, M-20503-007
www.amis.com
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