
AMIS-720442-A: 400dpi Contact Image Sensor
Data Sheet
12.0 Switching Characteristics at 25
°
C
The timing relationships of the video output voltage and its two input clocks the start pulse (SP) and the shift register clock, (CP), along
with the shift register (EOS) output clock are shown in Figure 11. The switch timing specification for the symbols on the timing diagram
is given in Table 9. The digital clocks' levels are +5V CMOS compatible. The video, IOUT, is specified in Figure 4, in Section 4.0.
Figure 11: Timing Diagram of the AMIS-720442-A Sensor
Table 9: Timing Symbol's Definition
Item
Clock cycle time
Clock pulse width
(1)
Clock duty cycle
Data setup time
Data hold time
Prohibit crossing time
(2)
EOS rise delay
EOS fall delay
Signal delay time
(3)
Signal settling time
(3)
Notes:
(1)
The cloc
(2)
Prohibit cro
its active high lev
Symbol
to
tw
tds
tdh
tprh
terdl
tefdl
tdl
ts/h
Minimum
200
50
25
20
20
Mean
50
20
60
70
20
120
Maximum
10000
75
Units
ns
ns
%
ns
ns
ns
ns
ns
ns
ns
k pulse width, tw, varie
ssing time is to insur
el when the CP
multiple SPs will load into the shift register.
Pixel delay times and settling times depend on the employment of the outp
12, using the AMIS-720442-A sensors. Note that the impulse signal current out of the device has pulse width ~ 30ns. Hence, the faster the amplifier with a
faster settling time will yield a signal video pulse with faster rise and settle times.
requency, as we
t no two SPs are lo
edges falls, the a tive high of the S
clock
s the duty cycle.
ed into the shift
ck
c
ter for any single scan time. Since the
nly during one falling, CP, cl
P is permitted o
s entered into the shift register during
s for any given scan. Otherwise,
ock edge
ut amplifier. These values, tdl and ts/h, are measured with the amplifier (see Figure
s with f
e tha
ll a
regis
SP i
(3)
13
AMI Semiconductor
– May 06, M-20571-001
www.amis.com