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| 型號： | AMIS-710650-A6 |
| 英文描述： | Color CIS Module Analog Video Output |
| 中文描述： | 彩色CIS模塊模擬視頻輸出 |
| 文件頁數(shù)： | 2/9頁 |
| 文件大?。?/td> | 204K |
| 代理商： | AMIS-710650-A6 |
AMIS-710650-A6: Color CIS Module
Data Sheet
Analog Video Output
5.0 Physical Overview
Table 2 describes a physical overview.
Table 2: Physical Overview
Parameter
Image sensors
Module outside dimension
Circuit power supply
Data output
Specification
AMIS-720058
Note
See image sensor data sheet
Figure 6
125mm x 18.9mm x 12.5mm
Typical 3.3V @ 50mA
One analog output
6.0 Recommended Operating Conditions
All tests were conducted at the typical pixel rate of 3.0MHz.
Table 3: Recommended Operating Conditions (25°C)
Parameter
Power supply
Video output level
Reference voltage input
Input voltage for digital high (input clocks, SP
and CP)
Input voltage for digital low (input clocks SS
and CP)
Clock frequency
Pixel frequency
Clock pulse high duty cycle
Clock pulse high duration
Integration time
Operating temperature
Notes:
(1)
VP represents the average value Vp(n) for all n in line scans, where n is the sequential number of a pixel. This signal pixel level should be operated at less than
saturation levels, i.e., <1.3V.
(2)
VREF is used to adjust the video output bias. Under normal operation it is left unconnected.
(3)
FREQ is the input clock (CP) frequency and the pixel rate (PRATE). The minimum rate for FREQ and PRATE should be consistent with the maximum TINT, see
Note 5.
(4)
DUTY is the ratio of the clock’s pulse width to its pulse period.
(5)
TINT is the time interval between two start pulses (SP). Hence, if SP is generated from a clock count down circuit, it will be directly proportional to the clock
frequency. There must be a minimum of (56+1204) clock cycles between the two SPs. The longest integration time is determined by the degree of leakage current
degradation that can be tolerated by the system. A 10ms maximum is a typical rule-of-thumb. An experienced CIS user can use his discretion to determine the
desired leakage tolerance level for the given system.
(6)
TOP is a conservative engineering estimate. It is based on measurements of similar CIS modules. In production, they are measured under standard QA practices,
that is, under the control of ISO 9000 standards.
Symbol
VDD
IDD
VP
(1)
VREF
(2)
VIH
Min.
0.15
3.2
Typ.
3.3
35
0.2
1.2
VDD
Max.
VDD +0.3
Units
V
mA
V
V
V
VIL
0
0.8
V
FREQ
(3)
PRATE
(3)
DUTY
(4)
TPW
TINT
(5)
TOP
(6)
0.50
0.50
200
~602
3.0
3.0
50
25
4.0
4.0
10000
50
MHz
MHz
%
ns
μs
C
2
AMI Semiconductor
– Aug. 06, M-20611-001
www.amis.com
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相關(guān)代理商/技術(shù)參數(shù) |
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