參數(shù)資料
型號(hào): AMIS-49200
英文描述: Fieldbus MAU Chip
中文描述: 現(xiàn)場總線MAU芯片
文件頁數(shù): 6/22頁
文件大?。?/td> 492K
代理商: AMIS-49200
AMIS-49200 Fieldbus MAU
Data Sheet
AMIS-49200
Fieldbus MAU
44 pin LQFP
22
21
20
19
18
17
16
15
14
13
12
34
35
36
37
38
39
40
41
42
43
44
1
2
3
5
6
7
33 32 31 30
26 25 24 23
29 28 27
VSS
VDRV
VSS
CRT
VCC
VDD
VO
SRTR
SRAO
SRSET
SRSETIN
RxA
RxS
TxE
TxS
POL
VSS
VSS
VSS
VSS
VSS
VCC
8
9 10 11
4
V
C
F
F
L
H
S
N
C
C
C
V
V
N
N
S
S
S
S
V
V
V
Pin Information
Figure 3: AMIS 49200 Fieldbus MAU Pin Out
Table 1: Pin Numbers and Signal Description
Signal Name
Pin No.
VSS
1
VREF
2
VMID
3
I/O (Note 1)
Ground
AO
AO
Description
Connect to ground
Internal bandgap voltage (1.18V)
2V bias voltage for AC signals
Power fail alarm at VCC input. This pin is an open-drain output of negative
logic.
Power fail alarm at VDD input. This pin is an open-drain output of negative
logic.
Feedback (non-inverting) input for the shunt regulator
Divided voltage of VCC input. Feeding this voltage to SHSETIN pin results in
5V voltage at VCC.
Control pin of the shunt regulator. Its sink current (25mA max) is controlled
so that the voltage at SHSETIN is equal to V
REF
(1.18V).
The current absorbed by SHUNT pin (25mA max) is fed to this pin, which
must be connected to the ground level
Ground
Ground
Feedback (inverting) input for the series regulator. The series regulator
controls its output (SRAO) to make this input voltage is equal to VREF
(1.18V).
Divided voltage of VO output. Feeding this voltage into SRSETIN pin results
in 3V at VO pin.
Output pin of an operational amplifier for the series regulator
Gate of a PMOS transistor for the series regulator
Output pin of the series regulator. (20mA max)
N_PFAIL1
4
AI/O
N_PFAIL2
5
AI/O
SHSETIN
6
AI
SHSET
7
AO
SHUNT
8
AI
VSS/
SGND
VSS
VSS
9
Ground
10
11
Ground
Ground
SRSETIN
12
AI
SRSET
13
AO
SRAO
SRTR
VO
14
15
16
AO
AI
AO
6
AMI Semiconductor
– Jan. 07, M-20532-003
www.amis.com
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