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參數(shù)資料
| 型號： | AME8500AEETAD21 |
| 廠商： | AME, Inc. |
| 英文描述： | Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset 16-SOIC -55 to 125 |
| 中文描述： | UProcessor監(jiān)督 |
| 文件頁數(shù)： | 10/14頁 |
| 文件大?。?/td> | 410K |
| 代理商： | AME8500AEETAD21 |
AME, Inc.
10
μ
Processor Supervisory
AME8500 / 8501
n
Timing Diagram
n
Applications Information
Supply Transients
These devices have a certain immunity to fast negative
going transients. In the following pages the graph titled
“Glitch Rejection” indicates the maximum allowable glitch
amplitude and duration to avoid triggering an unintended
reset. As shown in the graph shorter transients can have
larger amplitudes without triggering resets.
V
DD
RESETB
RESET
T
D2
V
Release
V
TH
T
D1
T
D2
T
D1
50%
50%
50%
50%
Glitch Rejection
Reset Time vs. Temperature
G
μ
S
Glitch Amplitude (V)
0
20
40
60
80
100
120
140
0.01
0.1
1
R
190
195
200
205
210
215
220
-45
-5
25
Temperature (
o
C)
55
85
115
AME8500AEETAF26
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AME8500AEETAD22 | Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset 16-SOIC -55 to 125 |
| AME8500AEETAD23 | Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset 16-SOIC -55 to 125 |
| AME8500AEETAD24 | UProcessor Supervisory |
| AME8500AEETAD26 | UProcessor Supervisory |
| AME8500AEETAD27 | UProcessor Supervisory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AME8500AEETAD22 | 制造商:AME 制造商全稱:Analog Microelectronics 功能描述:UProcessor Supervisory |
| AME8500AEETAD23 | 制造商:AME 制造商全稱:Analog Microelectronics 功能描述:UProcessor Supervisory |
| AME8500AEETAD24 | 制造商:AME 制造商全稱:Analog Microelectronics 功能描述:UProcessor Supervisory |
| AME8500AEETAD26 | 制造商:AME 制造商全稱:Analog Microelectronics 功能描述:UProcessor Supervisory |
| AME8500AEETAD27 | 制造商:AME 制造商全稱:Analog Microelectronics 功能描述:UProcessor Supervisory |
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