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參數(shù)資料
| 型號： | AMDDURON |
| 英文描述： | AMD Duron - AMD Duron Processor Model 3 Revision Guide |
| 中文描述： | AMD的毒龍- AMD的Duron處理器的型號3次指南 |
| 文件頁數(shù)： | 12/21頁 |
| 文件大?。?/td> | 183K |
| 代理商： | AMDDURON |
12
AMD Duron Processor Model 3 Revision Guide
23865K—October 2003
Preliminary Information
16
INVLPG Instruction Does Not Flush Entire Four-Megabyte Page Properly with Certain
Linear Addresses
Products Affected.
A0, A2
Normal Specified Operation.
After executing an INVLPG instruction the TLB should not contain any
translations for any part of the page frame associated with the designated logical address.
Non-conformance.
When the logical address designated by the INVLPG instruction is mapped by a 4-MB
page mapping and LA[21] is equal to one, it is possible that the TLB will still retain translations after
the instruction has finished executing.
Potential Effect on System.
The residual data in the TLB can result in unexpected data access to stale or
invalid pages of memory.
Suggested Workaround.
When using the INVLPG instruction in association with a page that is mapped via
a 4-MB page translation, always clear bit 21.
Resolution Status.
Fix planned for a future revision.
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