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參數(shù)資料
| 型號： | AMC80AIPWR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | POWER SUPPLY MANAGEMENT CKT, PDSO24 |
| 封裝： | GREEN, PLASTIC, TSSOP-24 |
| 文件頁數(shù)： | 7/23頁 |
| 文件大?。?/td> | 275K |
| 代理商： | AMC80AIPWR |
Input,
Temperature,
andFan
Watchdogs
Interrupt
Status
Registers
BTI
GPI/CI
INT_IN
Interrupt
Masking
and
Control
RST_OUTOS
/
OS Status:R06h,B0
INT
OS PinEnable:R05h,B6
RST Enable:R05h,B7
RESET:R00h,B4
TempWatchdog
OS Polarity:R06h,B1
INT Enable:R00h,B1
INTClear:R00h,B3
INTPolaritySelect:R00h,B2
SBOS559
– MAY 2011
INTERRUPT STRUCTURE
Figure 10 depicts the interrupt structure of the AMC80.
Figure 10. Interrupt Structure
External interrupt inputs can come from the following sources:
Board Temperature Interrupt (BTI) - This pin is an active low interrupt recommended to come from the
overtemperature shutdown (OS) output of TMP75 temperature sensors. The TMP75 OS output activates
when its temperature exceeds a programmed threshold. If the temperature of any TMP75 exceeds its
programmed limit, BTI is driven low. This action generates an interrupt through bit 1 of Interrupt Status
Register 2 (address 02h) that notifies the host of a possible overtemperature condition. To disable this
feature, set bit 1 of Interrupt Mask Register 2 (address 04h) to high. This pin also provides an internal, 10-k
Ω
pull-up resistor.
GPI/CI - This pin is an active high interrupt from any type of device that detects and captures chassis
intrusion violations. This action could be accomplished mechanically, optically, or electrically; circuitry external
to the AMC80 is expected to latch the event. Read this interrupt using bit 4 of Interrupt Status Register 2
(address 02h), and disable it using bit 4 of Interrupt Mask Register 2 (address 04h). The design of the AMC80
allows this input to go high even with no power applied, and no clamping or other interference with the line
occurs. This line can also be pulled low by the AMC80 for at least 10ms to reset a typical chassis-intrusion
circuit. Accomplish this reset by setting bit 5 of the Configuration Register (address 00h) to high; this bit is
self-clearing.
INT_IN - This pin is an active low interrupt that provides a way to connect an INT from other devices through
the AMC80 to the processor. If this pin is pulled low, then bit 7 of Interrupt Status Register 1 (address 01h)
goes high, indicating this interrupt detection. Setting bit 1 of the Configuration Register (address 00h) also
allows the INT pin to go low when INT_IN goes low. To disable this feature, set bit 7 of Interrupt Mask
Register 1 (address 03h) to high.
Device interrupt outputs can come from the following sources:
INT - This pin becomes active whenever INT_IN, BTI, or GPI/CI interrupts. INT is enabled when bit 1 of the
Configuration Register (address 00h) is set high. Bits 2 and 3 of the Configuration Register are also used to
set the polarity and state of the INT interrupt line.
OS - In the Fan Divisor/RST_OUT/OS Register (address 05h), bit 6 (OS Pin Enable), must be set high and bit
7 (RST Enable) must be set to low in order to enable the OS function on the RST_OUT/OS pin. The OS pin
has two modes of operation: One-Time Interrupt and Comparator. One-Time Interrupt mode is selected by
taking bit 2 of the OS Configuration/Temperature Resolution Register (address 06h) high. If bit 2 is taken low,
then Comparator mode is selected. Unlike the OS pin, the OS bit in Interrupt Status Register 2 (address 02h,
bit 5) functions in Default Interrupt and One-Time Interrupt modes. The OS bit can be masked to the INT pin
by taking bit 5 in Interrupt Mask Register 2 (address 04h) low.
Reading the Interrupt Status Registers (addresses 01h to 02h) outputs the contents and then resets the registers
and the INT pin. The INT pin is also cleared by the INT_Clear bit (address 00h, bit 3) without affecting the
contents of the Interrupt Status Registers. When this bit is high, the AMC80 monitoring loop is inactive;
monitoring resumes when this bit is low.
Copyright
2011, Texas Instruments Incorporated
15
Product Folder Link(s): AMC80
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