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| 型號： | AMC80AIPWR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | POWER SUPPLY MANAGEMENT CKT, PDSO24 |
| 封裝： | GREEN, PLASTIC, TSSOP-24 |
| 文件頁數(shù)： | 20/23頁 |
| 文件大?。?/td> | 275K |
| 代理商： | AMC80AIPWR |
SCL
SDA
t
(LOW)
t
R
t
F
t
(HDSTA)
t
(HDSTA)
t
(HDDAT)
t
(BUF)
t
(SUDAT)
t
(HIGH)
t
(SUSTA)
t
(SUSTO)
P
S
P
SBOS559
– MAY 2011
TIMING DIAGRAM
Figure 1. Serial Bus Interface Timing
TIMING CHARACTERISTICS
At TA –40°C to +125°C and VS = 3V to 5.5V, unless otherwise noted.
FAST MODE
HIGH-SPEED MODE
PARAMETER
MIN
MAX
MIN
MAX
UNITS
f(SCL)
SCL operating frequency
10
400
10
3400
kHz
t(BUF)
Bus free time between STOP and START conditions
600
160
ns
Hold time after repeated START condition. After this
t(HDSTA)
600
160
ns
period, the first clock is generated.
t(SUSTA)
Repeated START condition setup time
600
160
ns
t(SUSTO)
STOP condition setup time
600
160
ns
t(HDDAT)
Data hold time
0(1)
(2)
ns
t(SUDAT)
Data setup time
100
10
ns
t(LOW)
Clock low period
1300
160
ns
t(HIGH)
Clock high period
600
60
ns
tR
Clock/Data input rise time
300
160
ns
tF
Clock/Data input fall time
300
160
ns
(1)
For cases when the fall time of SCL is less than 20 ns and/or the rise time or fall time of SDA is less than 20 ns, the hold time should be
greater than 20 ns.
(2)
For cases when the fall time of SCL is less than 10 ns and/or the rise or fall time of SDA is less than 10 ns, the hold time should be
greater than 10 ns.
6
Copyright
2011, Texas Instruments Incorporated
Product Folder Link(s): AMC80
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