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參數(shù)資料
| 型號： | AMC0XXDFLKA |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 4, 8, 20, or 32 Megabyte 5.0 Volt-only Flash Memory PC Card |
| 中文描述： | 4，8，20或32兆字節(jié)5.0伏，只有閃存PC卡 |
| 文件頁數(shù)： | 43/46頁 |
| 文件大?。?/td> | 157K |
| 代理商： | AMC0XXDFLKA |
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AmC0XXDFLKA
43
CARD INFORMATION STRUCTURE
The D-Series card contains a separate EEPROM
memory for the Card Information Structure (CIS).
This allows all of the Flash memory to be used for the
common memory space. Part of the common memory
space could also be used to sore the CIS.
The EEPROM used in the D-Series card is designed
to operate from a 5 V single power supply. Table 9
shows the CIS information stored in the AMD Flash
memory card.
SYSTEM DESIGN AND INTERFACE
INFORMATION
Power Up and Power Down Protection
AMD’s Flash memory devices are designed to protect
against accidental programming or erasure caused by
spurious system signals that might exist during power
transitions. The AMD PC Card will power-up into a
READ mode when V
CC
is greater than V
LKO
of 3.2 V.
Erasing of memory sectors or memory segments can
be accomplished only by writing the proper Erase com-
mand to the card along with the proper Chip Enable,
Output Enable and Write Enable control signals. Hot in-
sertion of PC cards is not permitted by the PCMCIA
standard.
Note:
Hot insertion is defined as the socket condition
where the card is inserted or removed with any or
all of the following conditions present: V
CC
= V
CCH
,
V
PP
=V
PPH
, address and/or data lines are active.
System Power Supply Decoupling
The AMD Flash memory card has a 0.1
μ
F decoupling
capacitor between the V
CC
and the GND pins. It is rec-
ommended the system side also have a 4.7
μ
F capac-
itor between the V
CC
and the GND pins.
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| AMD-645 | Peripheral Bus Controller(外圍總線控制器) |
| AMD-751 | System Bus, System Memory Controller, AGP Controller, and PCI Bus Controller(系統(tǒng)總線、系統(tǒng)存儲(chǔ)器控制器、AGP控制器和PCI總線控制器) |
| AMD-756 | Peripheral Bus Controller(外圍總線控制器) |
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參數(shù)描述 |
|---|---|
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