參數(shù)資料
型號: AMC032DFLKA
廠商: ADVANCED MICRO DEVICES INC
元件分類: PROM
英文描述: 4, 8, 20, or 32 Megabyte 5.0 Volt-only Flash Memory PC Card
中文描述: 32M X 8 FLASH 5V PROM CARD, 150 ns, XMA68
文件頁數(shù): 3/46頁
文件大?。?/td> 157K
代理商: AMC032DFLKA
AmC0XXDFLKA
3
PC CARD PIN ASSIGNMENTS
Notes:
I = Input to card, O = Output from card
I/O = Bidirectional
NC = No connect
In systems which switch V
1. V
PP
not required for Programming or Reading operations.
2. BVD = Internally pulled-up.
3. Signal must not be connected between cards.
CC
individually to cards, no signal should be directly connected between cards other than ground.
Pin#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Signal
GND
D3
D4
D5
D6
D7
CE1
A10
OE
A11
A9
A8
A13
A14
WE
RY/BY
V
CC1
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
WP
GND
I/O
Function
Pin#
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
Signal
GND
CD1
D11
D12
D13
D14
D15
CE2
NC
NC
NC
A17
A18
A19
A20
A21
V
CC2
NC
A22
A23
A24
NC
NC
RESET
NC
NC
REG
BVD2
BVD1
D8
D9
D10
CD2
GND
I/O
Function
Ground
Data Bit 3
Data Bit 4
Data Bit 5
Data Bit 6
Data Bit 7
Card Enable 1 (Note 3)
Address Bit 10
Output Enable
Address Bit 11
Address Bit 9
Address Bit 8
Address Bit 13
Address Bit 14
Write Enable
Ready/Busy
Power Supply
No Connect (Note 1)
Address Bit 16
Address Bit 15
Address Bit 12
Address Bit 7
Address Bit 6
Address Bit 5
Address Bit 4
Address Bit 3
Address Bit 2
Address Bit 1
Address Bit 0
Data Bit 0
Data Bit 1
Data Bit 2
Write Protect (Note 3)
Ground
Ground
Card Detect 1 (Note 3)
Data Bit 11
Data Bit 12
Data Bit 13
Data Bit 14
Data Bit 15
Card Enable 2 (Note 3)
No Connect
No Connect
No Connect
Address Bit 17
Address Bit 18
Address Bit 19
Address Bit 20
Address Bit 21
Power Supply
No Connect (Note 1)
Address Bit 22
Address Bit 23
Address Bit 24
No Connect
No Connect
RESET
No Connect
No Connect
Register Select
Battery Vltg Detect 2 (Note 2)
Battery Vltg Detect 1 (Note 2)
Data Bit 8
Data Bit 9
Data Bit 10
Card Detect 2 (Note 3)
Ground
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
I
O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
O
I/O
I/O
I/O
O
I/O
I/O
I/O
O
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