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參數(shù)資料
| 型號： | AM85C30-16 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Enhanced Serial Communications Controller |
| 中文描述： | 增強的串行通信控制器 |
| 文件頁數(shù)： | 18/68頁 |
| 文件大?。?/td> | 553K |
| 代理商： | AM85C30-16 |
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AMD
18
Am85C30
Table 2. Register Addressing
“Point High”
Code In WR0:
D
2
, D
1
, D
0
In WR0:
Write
Register
Read
Register
D
/
C
High
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Either Way
Not True
Not True
Not True
Not True
Not True
Not True
Not True
Not True
True
True
True
True
True
True
True
True
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Data
0
1
2
3
4
5
6
7
Data
9
10
11
12
13
14
15
Data
0
1
2
3
(0)
(1)
(2)
(3)
Data
–
10
(15)
12
13
(10)
15
Read Registers
The ESCC contains eight Read registers [actually nine,
counting the receive buffer (RR8) in each channel]. Four
of these may be read to obtain status information (RR0,
RR1, RR10, and RR15). Two registers (RR12 and
RR13) may be read to learn the baud rate generator
time constant. RR2 contains either the unmodified inter-
rupt vector (Channel A) or the vector modified by status
information (Channel B). RR3 contains the Interrupt
Pending (IP) bits (Channel A). In addition, if bit D
2
of
WR15 is set, RR6 and RR7 are available for providing
frame status from the 10
×
19 bit Frame Status FIFO.
Figure 8 shows the formats for each Read register.
The status bits of RR0 and RR1 are carefully grouped to
simplify status monitoring, for example, when the inter-
rupt vector indicates a Special Receive Condition
interrupt, all the appropriate error bits can be
read from a single register (RR1). Please refer to
Am85C30 Technical Manual for detailed descriptions of
the read registers.
Write Registers
The ESCC contains 15 Write registers (16 counting
WR8, the transmit buffer) in each channel. These Write
registers are programmed separately to configure the
functional “personality” of the channels. Two registers
(WR2 and WR9) are shared by the two channels that
can be accessed through either of them. WR2 contains
the interrupt vector for both channels, while WR9 con-
tains the interrupt control bits. In addition, if bit D
0
of
WR15 is set, Write Register 7 prime (WR7
′
) is available
for programming additional SDLC/HDLC enhance-
ments. When bit D
0
of WR15 is set, executing a write to
WR7 actually writes to WR7
′
to further enhance the
functional “personality” of each channel. Figure 8 shows
the format of each Write register.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM85C30-8 | Enhanced Serial Communications Controller |
| AM85C30-8BQA | Enhanced Serial Communications Controller |
| AM8T-1203SC | 8 watt dc-dc converters |
| AM8T-1205DC | 8 watt dc-dc converters |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM85C30-16BQA | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Enhanced Serial Communications Controller |
| AM85C30-16BUA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM85C30-16DC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| AM85C30-16DCB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| AM85C30-16DIB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
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