參數(shù)資料
型號(hào): AM85C30-10
廠商: Advanced Micro Devices, Inc.
英文描述: Enhanced Serial Communications Controller
中文描述: 增強(qiáng)的串行通信控制器
文件頁數(shù): 49/68頁
文件大?。?/td> 553K
代理商: AM85C30-10
AMD
49
Am85C30
1
2
3
4
5
6
7
8
9
TwPCI
TwPCh
TfPC
TrPC
TcPC
TsA(WR)
ThA(WR)
TsA(RD)
ThA(RD)
TsIA(PC)
TsIA(WR)
PCLK Low Width
PCLK High Width
PCLK Fall Time
PCLK Rise Time
PCLK Cycle Time
Address to
WR
Setup Time
Address to
WR
Hold Time
Address to
RD
Setup Time
Address to
RD
Hold Time
I
NTACK
to PCLK
Setup Time
INTACK
to
WR
Setup Time
(Note 1)
INTACK
to
WR
Hold Time
INTACK
to
RD
Setup Time
(Note 1)
INTACK
to
RD
Hold Time
INTACK
to PCLK
Hold Time
CE
Low to
WR
Setup Time
CE
to
WR
Hold Time
CE
High to
WR
Setup Time
CE
Low to
RD
Setup Time
(Note 1)
CE
to
RD
Hold Time (Note1)
CE
High to
RD
Setup Time
(Note 1)
RD
Low Width (Note 1)
RD
to Read Data Active Delay
RD
to Read Data Not Valid Delay
RD
to Read Data Valid Delay
RD
to Read Data Float Delay
(Note 2)
50
50
1000
1000
15
15
2000
40
40
1000
1000
12
12
2000
26
26
1000
1000
8
8
2000
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
122
70
0
70
0
20
145
100
50
0
50
0
20
120
61
35
0
35
0
15
70
10
11
12
13
ThIA(WR)
TsIA(RD)
0
0
0
ns
ns
145
120
70
14
15
16
17
18
19
ThIAi(RD)
ThIA(PC)
TsCEI(WR)
ThCE(WR)
TsCEh(WR)
TsCEI(RD)
0
0
0
ns
ns
ns
ns
ns
ns
40
0
0
60
0
30
0
0
50
0
15
0
0
30
0
20
21
ThCE(RD)
TsCEh(RD)
0
0
0
ns
ns
60
50
30
22
23
24
25
26
TwRDI
TdRD(DRA)
TdRDr(DR)
TdRDf(DR)
TdRD(DRz)
150
0
0
125
0
0
75
0
0
ns
ns
ns
ns
ns
140
40
125
35
70
20
Notes:
1. Parameter does not apply to Interrupt Acknowledge transactions.
2. Float delay is defined as the time at which the data bus is released from its drive state with a maximum DC load and
minimum AC load.
No.
Parameter
Symbol
Parameter
Description
10 MHz
16.384 MHz
Min
Max
Min
Max
Unit
8.192 MHz
Min
Max
SWITCHING CHARACTERISTICS over MILITARY/INDUSTRIAL operating range
(continued)
Read and Write Timing (see Figure 21)
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