參數(shù)資料
型號(hào): AM85C30-10
廠商: Advanced Micro Devices, Inc.
英文描述: Enhanced Serial Communications Controller
中文描述: 增強(qiáng)的串行通信控制器
文件頁(yè)數(shù): 2/68頁(yè)
文件大?。?/td> 553K
代理商: AM85C30-10
AMD
2
Am85C30
Enhancements that allow the Am85C30 to be used
more effectively in high-speed applications include:
I
A 10
×
19 bit SDLC/HDLC frame status FIFO array
I
A 14-bit SDLC/HDLC frame byte counter
I
Automatic SDLC/HDLC opening frame flag
transmission
I
TxD pin forced High in SDLC NRZI mode after
closing flag
I
Automatic SDLC/HDLC Tx underrun/EOM flag
reset
I
Automatic SDLC/HDLC Tx CRC generator reset/
preset
I
RTS
synchronization to closing SDLC/HDLC flag
DTR
/
REQ
deactivation delay significantly reduced
I
External PCLK to
RxC
or
TxC
synchronization
requirement eliminated for PCLK divide-by-four
operation
Other enhancements to improve the Am85C30 inter-
face capabilities include:
I
Write data valid setup time to falling edge of
WR
requirement eliminated
I
Reduced
INT
response time
I
Reduced access recovery time (t
RC
) to 3 PCLK
best case (3 1/2 PCLK worst case)
I
Improved
Wait
timing
I
Write Registers WR3, WR4, WR5, and WR10
made readable
I
Lower priority interrupt masking without
INTACK
I
Complete SDLC/HDLC CRC character reception
BLOCK DIAGRAM
Data
Control
CPU
Bus VO
Internal
Control
Logic
Internal Bus
Channel
A
Registers
Interrupt
Control
Logic
Channel
B
Registers
+5 V GND PCLK
Channel A
Channel B
Control
Logic
Transmitter
Receiver
Baud
Rate
Generator
10
×
19 Bit
Frame
Status
FIFO
Interrupt
Control Lines
5
10216F-1
8
TxDA
RxDA
RTxCA
TRxCA
DTR/REQA
SYNCA
W/REQA
RTSA
CTSA
DCDA
TxDB
RxDB
RTxCB
TRxCB
DTR/REQB
SYNCB
W/REQB
RTSB
CTSB
DCDB
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