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參數(shù)資料
| 型號： | AM79C982 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | basic Integrated Multiport Repeater (bIMR) |
| 中文描述： | 基本綜合多端中繼器（bIMR） |
| 文件頁數(shù)： | 8/26頁 |
| 文件大小： | 254K |
| 代理商： | AM79C982 |
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1–10
Am79C982
P R E L I M I N A R Y
JAM
Jam
Input/Output/3-State
When JAM is asserted, the state of DAT will indicate
either a multiport (DAT = 0) or single-port (DAT = 1) col-
lision condition.
When ACK is not asserted, JAM is in high impedance.
If REQ and ACK are both asserted, then JAM is an out-
put. If ACK is asserted and REQ not asserted, then
JAM is an input.
This pin needs to be either pulled up or pulled down
through a high-value resistor.
REQ
Request
Output, Active LOW
This pin is driven LOW when the
b
IMR chip is active when it has one or more ports re-
ceiving or colliding or is in the state where it is still
transmitting data from the internal FIFO. The assertion
of this signal signifies that the
ing the use of the DAT and JAM lines for the transfer of
repeated data or collision status to other
RST
Reset
Input, Active LOW
Driving this pin LOW resets the internal logic of the
b
IMR device. Reset should be synchronized to the X
clock if either expansion or port activity monitor is used.
RXD+
0–7
, RXD–
0–7
(RXD+
0–3
, RXD–
0–3
)
Receive Data
Input
10BASE-T port differential receive inputs (4 or 8 ports).
SCLK
Serial Clock
Input
In normal operating mode, serial data (input or output)
is clocked (in or out) on the rising edge of the signal on
this pin. SCLK is asynchronous to X
1
and can operate
up to 10 MHz. In Minimum mode, this pin, together with
the SI pin, controls which information is output on the
SO pin.
SI
Serial In
Input
In normal operating mode, the SI pin is used for test/
management serial input port. Management com-
mands are clocked in on this pin synchronous to the
SCLK input. In Minimum mode, this pin, together with
the SCLK pin, controls which information is output on
the SO pin.
b
IMR chip is active. A
b
IMR device is request-
b
IMR devices.
1
In Minimum mode, the state of SI at the deassertion of
RST signal determines the programming of automatic
polarity detection/correction for 10BASE-T ports.
SO
Serial Out
Output
In normal operating mode, the SO pin is used for test/
management serial output port. Management results
are clocked out on this pin synchronous to the SCLK
input. In Minimum mode, the SO pin is used to output
the various status information serially based on the
state of the SI and SCLK pins.
STR
Store
Output
The STR pin goes HIGH for two X
1
clock cycle times
after the nine carrier sense bits are output on the CRS
pin. Note that the carrier sense signals arriving from
each port are latched internally, so that an active tran-
sition is remembered between samples.
TEST
Test Pin
Input, Active HIGH
This pin should be tied LOW for normal operation. If
this pin is driven HIGH, then the
b
IMR device can be
programmed for Loopback Test mode. Also, if this pin is
HIGH when the RST pin is deasserted, the
b
IMR de-
vice will enter the Minimum mode. An inverted version
of the RST signal can be used to program the device
into the Minimum mode.
SCLK
SI
SO Output
0
0
TP Ports Receive Polarity Status + AUI
SQE Test Error Status
0
1
Bit Rate Error (all ports)
1
0
TP Ports Link Status + AUI Loopback
Status
1
1
Port Partitioning Status (all ports)
Test
SI
Functions
0
0
Normal Management Mode
0
1
Normal Management Mode
1
0
Minimum Mode, Receive
Polarity Correction Disabled
1
1
Minimum Mode, Receive
Polarity Correction Enabled
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