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參數(shù)資料
| 型號： | AM79C982 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | basic Integrated Multiport Repeater (bIMR) |
| 中文描述： | 基本綜合多端中繼器（bIMR） |
| 文件頁數(shù)： | 12/26頁 |
| 文件大小： | 254K |
| 代理商： | AM79C982 |
AMD
PRELIMINARY
1–14
Am79C982
Expansion Port
The bIMR chip Expansion Port is comprised of five pins;
two are bi-directional signals (DAT and JAM), two are in-
put signals (
ACK
and
COL
), and one is an output signal
(
REQ
). These signals are used when a multiple-bIMR
device repeater application is employed. In this configu-
ration, all bIMR chips must be clocked synchronously
with a common clock connected to the X1 inputs of all
bIMR devices. Reset needs to be synchronized to
X1 clock.
The bIMR device expansion scheme allows the use of
multiple bIMR chips in a single board repeater or a
modular multiport repeater with a backplane architec-
ture. The DAT pin is a bidirectional I/O pin which can be
used to transfer data between the bIMR devices in a
multiple-bIMR chip design. The data sent over the DAT
line is in NRZ format and is synchronized to the common
clock. The JAM pin is another bidirectional I/O pin that is
used by the active bIMR chip to communicate its internal
status to the remaining (inactive) bIMR devices. When
JAM is asserted HIGH, it indicates that the active bIMR
device has detected a collision condition and is generat-
ing Jam Sequence. During this time when JAM is as-
serted HIGH, the DAT line is used to indicate whether
the active bIMR chip is detecting collision on one port
only or on more than one port. When DAT is driven
HIGH by the bIMR chip (while JAM is asserted by the
bIMR chip), then the active bIMR device is detecting a
collision condition on one port only. This ‘one-port-left’
signaling is necessary for a multiple-bIMR device re-
peater to function correctly as a single multiport repeater
unit. The bIMR chip also signals the ‘one port left’ colli-
sion condition in the event of a runt packet or collision
fragment; this signal will continue for one expansion port
bus cycle (100 ns) before deasserting
REQ
.
The arbitration for access to the bussed bi-directional
signals (DAT and JAM) is provided by one output (
REQ
)
and two inputs (
ACK
and
COL
). The bIMR chip asserts
the
REQ
pin to indicate that it is active and wishes to
drive the DAT and JAM pins. An external arbiter senses
the
REQ
lines from all the bIMR devices and asserts the
ACK
line when one and only one bIMR chip is asserting
its
REQ
line. If more than one bIMR chip is asserting its
REQ
line, the arbiter must assert the
COL
signal, indi-
cating that more than one bIMR device is active. More
than one active bIMR device at a time constitutes a colli-
sion condition, and all bIMR devices are notified of this
occurence via the
COL
line of the Expansion Port.
Note that a transition from multiple bIMR devices arbi-
trating for the DAT and JAM pins (with
COL
asserted,
ACK
deasserted) to a condition when only one bIMR
chip is arbitrating for the DAT and JAM pins (with
ACK
asserted,
COL
deasserted) involves one expansion port
bus cycle (100 ns). During this transitional bus cycle,
COL
is deasserted,
ACK
is asserted, and the DAT and
JAM pins are not driven. However, each bIMR device
will remain in the collision state (transmitting jam se-
quence) during this transitional bus cycle. In subse-
quent expansion port bus cycles (
REQ
and
ACK
still
asserted), the bIMR devices will return to the ‘master
and slaves’ condition where only one bIMR device is ac-
tive (with collision) and is driving the DAT and JAM pins.
An understanding of this sequence is crucial if non-
bIMR devices (such as an Ethernet controller) are con-
nected to the expansion bus. Specifically, the last
device to back off of the Expansion Port after a multi-
bIMR chip collision must assert the JAM line until it too
drops its request for the Expansion Port.
External Arbiter
A simple arbitration scheme is required when multiple
bIMR devices are connected together to increase the to-
tal number of repeater ports. The arbiter should have
one input (
REQ1
...
REQn
) for each of the n bIMR de-
vices to be used, and two global outputs (
COL
and
ACK
). This function is easily implemented in a PAL
de-
vice, with the following logic equations:
ACK =
REQ1 &
REQ2
&
REQ3
& ....
REQn
REQ1
& REQ2 &
REQ3
& ....
REQn
+
+
REQ1
&
REQ2
&
REQ3
& .... REQn
ACK
& (REQ1 + REQ2 + REQ3 + ... REQn)
COL =
Above equations are in positive logic, i.e., a variable is
true when asserted.
A single PALCE16V8 will perform the arbitration func-
tion for a repeater based on several bIMR devices.
相關PDF資料 |
PDF描述 |
|---|---|
| AM79C982-4JC | basic Integrated Multiport Repeater (bIMR) |
| AM79C982-8JC | basic Integrated Multiport Repeater (bIMR) |
| AM79C983AKC | Integrated Multiport Repeater 2 (IMR2⑩) |
| AM79C984 | enhanced Integrated Multiport Repeater (eIMR⑩) |
| AM79C984A | enhanced Integrated Multiport Repeater (eIMR⑩) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C982-4JC | 制造商:Advanced Micro Devices 功能描述:LAN HUB CONTROLLER, 84 Pin, PLCC |
| AM79C982-8JC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:basic Integrated Multiport Repeater (bIMR) |
| AM79C983 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Am79C983 Datasheet? 348KB (PDF) Integrated Multiport Repeater 2 IMR2 ? |
| AM79C983A | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Integrated Multiport Repeater 2 (IMR2⑩) |
| AM79C983AKC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Integrated Multiport Repeater 2 (IMR2⑩) |
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