參數(shù)資料
型號(hào): AM79C981JC
廠商: ADVANCED MICRO DEVICES INC
元件分類: 網(wǎng)絡(luò)接口
英文描述: Integrated Multiport Repeater Plus⑩ (IMR+⑩)
中文描述: DATACOM, ETHERNET TRANSCEIVER, PQCC84
封裝: PLASTIC, LCC-84
文件頁數(shù): 20/40頁
文件大?。?/td> 347K
代理商: AM79C981JC
AMD
PRELIMINARY
1–90
Am79C981
Am79C981
IMR+ Chip
XTAL
OSC
CK
D
Q
ASYNC
RESET
X1
X2
RST
STR
SO
CLR
CK
Q
Q
D
1/2 ’74
TCK
CK
SI
SIPO
CK
T
P
7
T
P
6
T
P
5
T
P
0
17306B-7
A
U
I
1/2 ’74
TCK
SCLK
SI
Register
TEST
Figure 3. Minimum Mode, Non-Intelligent Repeater Example
X1
CRS
(Note 2)
STR
CRS
AUI
CRS
TP0
CRS
TP1
CRS
TP2
CRS
TP3
CRS
TP4
CRS
TP5
CRS
TP6
CRS
TP7
CRS
AUI
TCK
(Note 1)
SO
(Note 3)
SO
AUI
SO
TP0
SO
TP1
SO
TP2
SO
TP3
SO
TP4
SO
TP5
SO
TP6
SO
TP7
SO
AUI
17306B-8
Notes:
1. Externally generated signal illustrates internal IMR+ chip clock phase relationship.
2. CRS timing with the C-bit cleared (IMR+ Chip Programmable Options)
3. For Minimum Hub Mode
Figure 4. Management Port Minimum Mode and
Port Activity Monitor Signal Relationship
Port Activity Monitor
Two pins, CRS and STR, are used to serially output the
state of the internal Carrier Sense signals from the AUI
and the eight TP ports. This function together with exter-
nal hardware and/or software can be used to monitor re-
peater receive and/or collision activity.
The following diagram shows typical external hardware
employed to convert the serial bit stream into parallel
form. The accuracy of the CRS signals is 10 Bit Times
(BT) (1
μ
s). Specifically, a transition to active state by
any of the internal carrier sense bits that lasts for less
than 10BT is latched internally and is used to set the ap-
propriate bit during the next sample period.
相關(guān)PDF資料
PDF描述
AM79C982 basic Integrated Multiport Repeater (bIMR)
AM79C982-4JC basic Integrated Multiport Repeater (bIMR)
AM79C982-8JC basic Integrated Multiport Repeater (bIMR)
AM79C983AKC Integrated Multiport Repeater 2 (IMR2⑩)
AM79C984 enhanced Integrated Multiport Repeater (eIMR⑩)
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