參數(shù)資料
型號(hào)： AM79C961AKC
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
中文描述： 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP13
封裝： CARRIER RING, PLASTIC, QFP-132
文件頁(yè)數(shù)： 56/85頁(yè)
文件大小： 1088K
代理商： AM79C961AKC
56
Am79C961A
P R E L I M I N A R Y
transfers in that cycle. The general rule is that the
longer the Bus Grant latency or the slower the bus
transfer operations (or clock speed) or the higher the
transmit watermark or the lower the receive watermark
or any combination thereof, the longer will be the aver-
age bus mastership period.
Buffer Management Unit (BMU)
The buffer management unit is a microcoded 20 MHz
state machine which implements the initialization block
and the descriptor architecture.
Initialization
PCnet-ISA II controller initialization includes the read-
ing of the initialization block in memory to obtain the
operating parameters. The initialization block is read
when the INIT bit in CSR0 is set. The INIT bit should be
set before or concurrent with the STRT bit to insure cor-
rect operation. See previous section “1. Initialization
Block DMA Transfer.” Once the initialization block has
been read in and processed, the BMU knows where
the receive and transmit descriptor rings are. On com-
pletion of the read operation and after internal registers
have been updated, IDON will be set in CSR0, and an
interrupt generated if IENA is set.
The Initialization Block is vectored by the contents of
CSR1 (least significant 16 bits of address) and CSR2
(most significant 8 bits of address). The block contains
the user defined conditions for PCnet-ISA II controller
operation, together with the address and length infor-
mation to allow linkage of the transmit and receive
descriptor rings.
There is an alternative method to initialize the
PCnet-ISA II controller. Instead of initialization via the
initialization block in memory, data can be written
directly into the appropriate registers. Either method
may be used at the discretion of the programmer. If the
registers are written to directly, the INIT bit must not be
set, or the initialization block will be read in, thus over-
writing the previously written information. Please refer
to Appendix D for details on this alternative method.
Reinitialization
The transmitter and receiver section of the PCnet-ISA
II controller can be turned on via the initialization block
(MODE Register DTX, DRX bits; CSR15[1:0]). The
state of the transmitter and receiver are monitored
through CSR0 (RXON, TXON bits). The PCnet-ISA II
controller should be reinitialized if the transmitter and/
or the receiver were not turned on during the original
initialization and it was subsequently required to acti-
vate them, or if either section shut off due to the detec-
tion of an error condition (MERR, UFLO, TX BUFF
error).
Reinitialization may be done via the initialization block
or by setting the STOP bit in CSR0, followed by writing
to CSR15, and then setting the START bit in CSR0.
Note that this form of restart will not perform the same
in the PCnet-ISA II controller as in the LANCE. In par-
ticular, the PCnet-ISA II controller reloads the transmit
and receive descriptor pointers (working registers) with
their respective base addresses. This means that the
software must clear the descriptor’s own bits and reset
its descriptor ring pointers before the restart of the
PCnet-ISA controller. The reload of descriptor base
addresses is performed in the LANCE only after initial-
ization, so a restart of the LANCE without initialization
leaves the LANCE pointing at the same descriptor
locations as before the restart.
Suspend
The PCnet-ISA II controller offers a suspend mode that
allows easy updating of the CSR registers without
going through a full reinitialization of the device. The
suspend mode also allows stopping the device with
orderly termination of all network activity.
The host requests the PCnet-ISA II controller to enter
the suspend mode by setting SPND (CSR5, bit 0) to
ONE. The host must poll SPND until it reads back ONE
to determine that the PCnet-ISA II controller has en-
tered the suspend mode. When the host sets SPND to
ONE, the PCnet-ISA II controller first finishes all
on-going transmit activity and updates the correspond-
ing transmit descriptor entries. It then finishes all
on-going receive activity and updates the correspond-
ing receive descriptor entries. It then sets the
read-version of SPND to ONE and enters the suspend
mode. In suspend mode, all of the CSR registers are
accessible. As long as the PCnet-ISA II controller is not
reset while in suspend mode (by asserting the RESET
pin, reading the RESET register, or by setting the
STOP bit), no reinitialization of the device is required
after the device comes out of suspend mode. When
SPND is set to ZERO, the PCnet-ISA II controller will
leave the suspend mode and will continue at the trans-
mit and receive descriptor ring locations where it had
left when it entered the suspend mode.
Buffer Management
Buffer management is accomplished through message
descriptor entries organized as ring structures in mem-
ory. There are two rings, a receive ring and a transmit
ring. The size of a message descriptor entry is 4 words
(8 bytes).
Descriptor Rings
Each descriptor ring must be organized in a contiguous
area of memory. At initialization time (setting the INIT
bit in CSR0), the PCnet-ISA II controller reads the
user-defined base address for the transmit and receive
descriptor rings, which must be on an 8-byte boundary,
as well as the number of entries contained in the
descriptor rings. By default, a maximum of 128 ring
entries is permitted when utilizing the initialization
block, which uses values of TLEN and RLEN to specify
相關(guān)PDF資料
PDF描述
AM79C961A PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
AM79C961AKIW PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
AM79C961AVCW PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
AM79C961AVIW PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
Am79C965A PCnet?-32 Single-Chip 32-Bit Ethernet Controller
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C961AKC/W 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller
AM79C961AKCW 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
AM79C961AKI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller
AM79C961AKI/W 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller
AM79C961AKIW 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*