參數(shù)資料
型號: AM79C90JCTR
廠商: ADVANCED MICRO DEVICES INC
元件分類: 微控制器/微處理器
英文描述: KPTC6CG10-6P
中文描述: 1 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQCC68
封裝: PLASTIC, LCC-68
文件頁數(shù): 15/62頁
文件大?。?/td> 437K
代理商: AM79C90JCTR
P R E L I M I N A R Y
AMD
1
5
Am79C90
DAL0–DAL15
DAS
READ
READY
(Output from
C-LANCE)
HOLD
CS
ADR
17881B-10
Write Data
O.D.
Figure 4. Bus Slave Write Timing
Read Sequence (Master Mode)
A read cycle is begun by placing a valid address on
DAL00 – DAL15 and A16 – A23. The BYTE MASK sig-
nals are asserted to indicate a word, upper byte or lower
byte memory reference. READ indicates the type of cy-
cle. ALE or
AS
is pulsed, and the trailing edge of either
can be used to latch addresses. DAL00 – DAL15 go into
a 3-state mode, and
DAS
falls LOW to signal the begin-
ning of the memory access. The memory responds by
placing
READY
LOW to indicate that the DAL lines have
valid data. The C-LANCE then latches memory data on
the rising edge of
DAS
, which in turn ends the memory
cycle and
READY
returns HIGH. Refer to Figure 5-1.
The bus transceiver controls,
DALI
and
DALO
, are used
to control the bus transceivers.
DALI
directs data toward
the C-LANCE, and
DALO
directs data or addresses
away from the C-LANCE. During a read cycle,
DALO
goes inactive before
DALI
becomes active to avoid
“spiking” of the bus transceivers.
Write Sequence (Master Mode)
The write cycle is similar to the read cycle except that the
DAL00 – DAL15 lines change from containing ad-
dresses to data after either ALE or
AS
goes inactive.
After data is valid on the bus,
DAS
goes active. Data to
memory is held valid after
DAS
goes inactive. Refer to
Figure 5-2.
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