參數(shù)資料
型號(hào)： Am70PDL129CDH66IT
廠商： Advanced Micro Devices, Inc.
英文描述： 2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS
中文描述： 2 × 64兆位（8米× 16位）的CMOS 3.0伏特，只有頁面模式閃存數(shù)據(jù)存儲(chǔ)128兆位（8米× 16位）的CMOS
文件頁數(shù)： 122/127頁
文件大?。?/td> 849K
代理商： AM70PDL129CDH66IT
120
Am70PDL127CDH/Am70PDL129CDH
November 24, 2003
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Alternate CE# Controlled Erase and Program Operations
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
3. For 1–16 words/1–32 bytes programmed.
4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation.
5. Word/Byte programming specification is based upon a single word/byte programming operation not utilizing the write buffer.
6. AC Specifications listed are tested with V
IO
= V
CC
. Contact AMD for information on AC operation with V
IO
≠
V
CC
.
Parameter
Speed Options
JEDEC
Std.
Description
Unit
t
AVAV
t
WC
Write Cycle Time (Note 1)
Min
110
ns
t
AVWL
t
AS
Address Setup Time
Min
0
ns
t
ELAX
t
AH
Address Hold Time
Min
45
ns
t
DVEH
t
DS
Data Setup Time
Min
45
ns
t
EHDX
t
DH
Data Hold Time
Min
0
ns
t
GHEL
t
GHEL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
t
WLEL
t
WS
WE# Setup Time
Min
0
ns
t
EHWH
t
WH
WE# Hold Time
Min
0
ns
t
ELEH
t
CP
CE# Pulse Width
Min
45
ns
t
EHEL
t
CPH
CE# Pulse Width High
Min
30
ns
t
WHWH1
t
WHWH1
Write Buffer Program Operation (Notes 2, 3)
Typ
352
μs
Effective Write Buffer Program
Operation (Notes 2, 4)
Per Word
Typ
22
μs
μs
Accelerated Effective Write Buffer
Program Operation (Notes 2, 4)
Per Word
Typ
17.6
μs
μs
Single Word/Byte Program
Operation (Note 2, 5)
Word
Typ
100
μs
Single Word/Byte Accelerated
Programming Operation (Note 2,
5)
Word
Typ
90
μs
t
WHWH2
t
WHWH2
Sector Erase Operation (Note 2)
Typ
0.5
sec
t
RH
RESET# High Time Before Write
Min
50
ns
相關(guān)PDF資料
PDF描述
Am70PDL129CDH85IS 2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS
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