參數(shù)資料
型號: AM53C94JC
廠商: ADVANCED MICRO DEVICES INC
元件分類: 總線控制器
英文描述: High Performance SCSI Controller
中文描述: SCSI BUS CONTROLLER, PQCC84
封裝: PLASTIC, LCC-84
文件頁數(shù): 35/63頁
文件大小: 455K
代理商: AM53C94JC
P R E L I M I N A R Y
AMD
35
Am53C94/Am53C96
After the device has received the last byte of message, it
keeps the
ACK
signal asserted. This allows the device
to either accept or reject the message. To accept the
message, Message Accepted Command is issued. To
reject the message the
ATN
signal must be asserted
(with the help of the Set
ATN
Command) before issuing
the Message Accepted Command. In either case the
Message Accepted Command has to be issued to re-
lease the
ACK
signal.
Transfer Pad Bytes Command
(Command Code 18H/98H)
The Transfer Pad Bytes Command is used to recover
from an error condition. This command is similar to the
Information Transfer Command, only the information
bytes consists of null data. It is used when the target ex-
pects more data bytes than the initiator has to send. It is
also used when the initiator receives more information
than it expected from the target.
When sending data to the SCSI bus, the FIFO is loaded
with null bytes and these bytes are sent out to the SCSI
bus. DMA has to be enabled when pad bytes are trans-
ferred to the SCSI bus. No actual DMA requests are
made but the device uses the Current Transfer Count
Register (CTCREG) 00H–01H to terminate the
transfer.
When receiving data from the SCSI bus, the device will
receive the pad bytes and place them on the top of the
FIFO and unload them from the bottom of the FIFO.
The command terminates under the same condition as
the Information Transfer Command, only the device
does not keep the
ACK
signal asserted during the last
byte of the Message In phase. If this command termi-
nates prematurely, due to a disconnect or a phase
change, before the CTCREG decrements to zero, the
FIFO may contain residual pad bytes.
Set
ATN
Command (Command Code 1AH)
The Set
ATN
Command is used to drive the
ATN
signal
active on the SCSI bus. An interrupt is not generated at
the end of this command. The
ATN
signal is deasserted
before asserting the
ACK
signal during the last byte of
the Message Out phase.
Note:
The
ATN
signal is asserted by the device without this
command in the following cases:
I
If any select with
ATN
command is issued and the
arbitration is won.
I
An initiator needs the target’s attention to send a
message. The
ATN
signal is asserted before deas-
serting the
ACK
signal.
Reset
ATN
Command (Command Code 1BH)
The Reset
ATN
Command is used to deassert the
ATN
signal on the SCSI bus. An interrupt is not generated at
the end of this command. This command is used only
when interfacing with devices that do not support the
Common Command Set (CCS). These older devices do
not deassert their
ATN
signal automatically on the last
byte of the Message Out phase. This device does deas-
sert its
ATN
signal automatically on the last byte of the
Message Out phase.
Target Commands
Target commands are executed by the device when it is
in the target mode. If the device is not in the target mode
and a target command is received the device will ignore
the command, generate an illegal command interrupt
and clear the Command Register (CMDREG) 03H.
A SCSI bus reset during any target command will cause
the device to abort the command sequence , flag a SCSI
bus reset interrupt (if the interrupt is enabled) and dis-
connect from the SCSI bus.
Normal or successful completion of a target command
will cause a Successful Operation interrupt to be
flagged. If the
ATN
signal is asserted during a target
command sequence the Service Request bit is asserted
in the Interrupt Status Register (INSTREG) 05H. If the
ATN
signal is asserted when the device is in an idle state
a Service Request interrupt will be generated, the Suc-
cessful Operation bit in the INSTREG will be reset and
the CMDREG cleared.
Send Message Command
(Command Code 20H/A0H)
The Send Message Command is used by the target to
inform the initiator to receive a message. The SCSI bus
phase lines are set to the Message In Phase and mes-
sage bytes are transferred from the device FIFO to the
buffer memory.
Send Status Command
(Command Code 21H/A1H)
The Send Status Command is used by the target to in-
form the initiator to receive status information. The SCSI
bus phase lines are set to the Status Phase and status
bytes are transferred from the target device to the initia-
tor device.
Send Data Command (Command Code 22H/A2H)
The Send Data Command is used by the target to inform
the initiator to receive data bytes. The SCSI bus phase
lines are set to the Data-In Phase and data bytes are
transferred from the target device to the initiator device.
Disconnect Steps Command
(Command Code 23H/A3H)
The Disconnect Steps Command is used by the target to
disconnect from the SCSI bus. This command consists
of two steps. The first step consists of sending two bytes
of the Save Data Pointers commands by the target in the
Message In Phase. In the second step the target discon-
nects from the SCSI bus. Successful Operation and Dis-
connected bits are set in the Interrupt Status Register
(INSTREG) 05H upon command completion. If
ATN
sig-
nal is asserted by the initiator then Successful Operation
and Service Request bits are set in the INSTREG, the
CMDREG is cleared and Disconnect Steps Command
terminates without disconnecting.
相關(guān)PDF資料
PDF描述
AM53C96KC High Performance SCSI Controller
AM53C96KCW High Performance SCSI Controller
AM53C94 Intergrated Optical Disk Controller
AM80C186 Circular Connector; No. of Contacts:3; Series:MS27508; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:12; Circular Contact Gender:Pin; Circular Shell Style:Box Mount Receptacle; Insert Arrangement:12-3 RoHS Compliant: No
AM80C286 Circular Connector; No. of Contacts:10; Series:MS27508; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:12; Circular Contact Gender:Socket; Circular Shell Style:Box Mount Receptacle RoHS Compliant: No
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM53C96 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Intergrated Optical Disk Controller
AM53C96KC 制造商:Advanced Micro Devices 功能描述:BUS Controller Circuit, 100 Pin, TQFP
AM53C96KCW 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:High Performance SCSI Controller
AM53C974KC/W 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SCSI Bus Interface/Controller
AM53CF94 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Enhanced SCSI-2 Controller (ESC)