參數(shù)資料
型號: AM50DL128BH85IS
廠商: Advanced Micro Devices, Inc.
元件分類: SRAM
英文描述: Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
中文描述: 堆疊式多芯片封裝(MCP)閃存和SRAM
文件頁數(shù): 46/68頁
文件大?。?/td> 959K
代理商: AM50DL128BH85IS
44
Am50DL128BH
October 7, 2003
A D V A N C E I N F O R M A T I O N
FLASH AC CHARACTERISTICS
Hardware Reset (RESET#)
Note:
Not 100% tested.
Parameter
Description
All Speed Options
Unit
JEDEC
Std
t
Ready
RESET# Pin Low (During Embedded Algorithms)
to Read Mode (See Note)
Max
20
μ
s
t
Ready
RESET# Pin Low (NOT During Embedded
Algorithms) to Read Mode (See Note)
Max
500
ns
t
RP
RESET# Pulse Width
Min
500
ns
t
RH
Reset High Time Before Read (See Note)
Min
50
ns
t
RPD
RESET# Low to Standby Mode
Min
20
μ
s
t
RB
RY/BY# Recovery Time
Min
0
ns
RESET#1,
RESET#2
RY/BY#1,
RY/BY#2
RY/BY#1,
RY/BY#2
t
RP
t
Ready
Reset Timings NOT during Embedded Algorithms
t
Ready
CE#f, OE#
t
RH
CE#f, OE#
Reset Timings during Embedded Algorithms
RESET#1,
RESET#2
t
RP
t
RB
Figure 16.
Reset Timings
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