參數(shù)資料
型號(hào): AM49DL32XBG
英文描述: Am49DL32xBG - Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
中文描述: Am49DL32xBG -堆疊式多芯片封裝(MCP)閃存和SRAM
文件頁(yè)數(shù): 11/62頁(yè)
文件大?。?/td> 933K
代理商: AM49DL32XBG
September 19, 2003
Am49DL3208G
9
A D V A N C E I N F O R M A T I O N
ORDERING INFORMATION
The order number (Valid Combination) is formed by the following:
Valid Combinations
Valid Combinations list configurations planned to be supported in vol-
ume for this device. Consult the local AMD sales office to confirm
availability of specific valid combinations and to check on newly re-
leased combinations.
MCP DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Tables
1
-
3
lists the device bus operations, the
inputs and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Am49DL320
8
G
T
71
I
T
TAPE AND REEL
T
=
S
=
7 inches
13 inches
TEMPERATURE RANGE
I
=
Industrial (–40
°
C to +85
°
C)
SPEED OPTION
See Product Selector Guide and Valid Combinations
BOOT SECTOR
T
=
B
=
Top boot
Bottom boot
PROCESS TECHNOLOGY
G
=
0.17 μm
PSEUDO SRAM DEVICE DENSITY
8
=
8 Mbits
AMD DEVICE NUMBER/DESCRIPTION
Am49DL3208G
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
Am29DL320G 32 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash
Memory and 8 Mbit (512 K x 16-Bit) Pseudo Static RAM
Valid Combinations
Order Number
Package Marking
Am49DL3208GT70I
Am49DL3208GB70I
T, S
M490000032
M490000033
Am49DL3208GT71I
Am49DL3208GB71I
T, S
M490000034
M490000035
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