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| 型號： | AM49DL324BGB85 |
| 廠商： | Spansion Inc. |
| 英文描述： | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous |
| 中文描述： | 堆疊式多芯片封裝（MCP）閃存和SRAM的32兆位（4個M × 8位/ 2米x 16位），3.0伏的CMOS只，同時 |
| 文件頁數(shù)： | 32/64頁 |
| 文件大?。?/td> | 570K |
| 代理商： | AM49DL324BGB85 |
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July 19, 2002
Am49DL32xBG
31
P R E L I M I N A R Y
Table 16.
Command Definitions (Flash Byte Mode)
Legend:
X = Don
’
t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses
latch on the falling edge of the WE# or CE#f pulse, whichever happens
later.
PD = Data to be programmed at location PA. Data latches on the rising
edge of WE# or CE#f pulse, whichever happens first.
SADD = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A20
–
A12 uniquely select any sector.
BA = Address of the bank that is being switched to autoselect mode, is
in bypass mode, or is being erased.
Notes:
1.
2.
3.
See Table 1 for description of bus operations.
All values are in hexadecimal.
Except for the read cycle and the fourth cycle of the autoselect
command sequence, all bus cycles are write cycles.
Data bits DQ15
–
DQ8 are don
’
t care in command sequences,
except for RD and PD.
Unless otherwise noted, address bits A20
–
A12 are don
’
t cares.
No unlock or command cycles required when bank is in read
mode.
The Reset command is required to return to reading array data
(or to the erase-suspend-read mode if previously in Erase
Suspend) when a bank is in the autoselect mode, or if DQ5 goes
high (while the bank is providing status information).
The fourth cycle of the autoselect command sequence is a read
cycle. The system must provide the bank address to obtain the
manufacturer ID, device ID, or SecSi Sector factory protect
information. Data bits DQ15
–
DQ8 are don
’
t care. See the
Autoselect Command Sequence section for more information.
The data is 82h for factory locked and 02h for not factory locked.
10. The data is 00h for an unprotected sector/sector block and 01h
for a protected sector/sector block.
4.
5.
6.
7.
8.
9.
11. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
12. The Unlock Bypass Reset command is required to return to
reading array data when the bank is in the unlock bypass mode.
13. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation, and requires the bank address.
14. The Erase Resume command is valid only during the Erase
Suspend mode, and requires the bank address.
15. Command is valid when device is ready to read array data or when
device is in autoselect mode.
Table 17.
Autoselect Device IDs (Byte Mode)
T = Top Boot Sector, B = Bottom Boot Sector
Command
Sequence
(Note 1)
C
Bus Cycles (Notes 2
–
5)
Third
Addr
Data
First
Second
Addr
Fourth
Fifth
Sixth
Addr
RA
XXX
Data
RD
F0
Data
Addr
Data
Addr
Data
Addr
Data
Read (Note 6)
Reset (Note 7)
1
1
A
Manufacturer ID
4
AAA
AA
555
55
(BA)
AAA
(BA)
AAA
(BA)
AAA
(BA)
AAA
AAA
AAA
AAA
AAA
90
(BA) 00
01
Device ID
6
AAA
AA
555
55
90
(BA) 02
see
Table 17
SecSi
Sector Factory Protect
(Note 9)
Sector Protect Verify
(Note 10)
Enter SecSi Sector Region
Exit SecSi Sector Region
Program
Unlock Bypass
Unlock Bypass Program (Note 11)
Unlock Bypass Reset (Note 12)
Chip Erase
Sector Erase
Erase Suspend (Note 13)
Erase Resume (Note 14)
CFI Query (Note 15)
4
AAA
AA
555
55
90
(BA)
X06
(SADD)
X04
82/02
4
AAA
AA
555
55
90
00
01
3
4
4
3
2
2
6
6
1
1
1
AAA
AAA
AAA
AAA
XXX
XXX
AAA
AAA
BA
BA
55
AA
AA
AA
AA
A0
90
AA
AA
B0
30
98
555
555
555
555
PA
XXX
555
555
55
55
55
55
PD
00
55
55
88
90
A0
20
XXX
PA
00
PD
AAA
AAA
80
80
AAA
AAA
AA
AA
555
555
55
55
AAA
SADD
10
30
Device
Am29DL322G
Am29DL323G
Am29DL324G
Autoselect Device ID
55h (T), 56h (B)
50h (T), 53h (B)
5Ch (T), 5Fh (B)
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| AM49DL324BGT85 | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AM49DL324BGB85S | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 32 Mbit (2M x 16-Bit) |
| AM49DL324BGB85T | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 32 Mbit (2M x 16-Bit) |
| AM49DL324BGT70 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous |
| AM49DL324BGT70S | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 32 Mbit (2M x 16-Bit) |
| AM49DL324BGT70T | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 32 Mbit (2M x 16-Bit) |
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